I-Corps: Customizable and scalable high-performance microprocessor

这个I-Corps项目的更广泛的影响/商业潜力是为成本敏感的嵌入式处理器提供上级性能和能效。 随着计算设备变得无处不在并渗透到生活的各个方面，对更高性能的需求也随之而来。 然而，使能高性能微处理器的传统设计技术招致资源成本并且通常遭受差的能量效率。 这些开销的成本相当高，因为大多数嵌入式设计都是能源受限且对成本高度敏感的。 这些相互竞争的设计约束的副产品已经由于传统技术的无效而停滞了进展。通过使用该项目的新型处理器微体系结构，商业设计应该观察到大约30%的更高的能源效率和上级性能，而不会产生资源开销。网络和存储领域等应用是采用该设计的最初候选者。该I-Corps项目的重点是通过使用新型处理器微架构来创建节能微控制器。 在大多数基本微处理器技术发展的时候，功率不是问题，晶体管也很稀缺。 为了满足这些约束，设计集中在最大限度地利用现有的少数执行资源。 随着晶体管变得越来越丰富，性能变得越来越重要，设计利用这些额外的晶体管来实现复杂的组织和调度技术，以最大限度地利用稀缺的执行资源。 该项目的架构通过为执行资源分配额外的晶体管并大大简化组织和调度开销来扭转这一趋势。 初步研究表明，与目前的商业设计相比，在保持高水平性能的同时，可以获得相当大的能源和面积效率收益。此外，该微处理器的新颖结构使得许多优化成为可能，这些优化在传统设计中由于其复杂的组织和调度而不切实际。

The broader impact/commercial potential of this I-Corps project is to enable superior performance and energy efficiency for cost-sensitive embedded processors. As computing devices have become ubiquitous and permeated every aspect of life, the need for greater performance has also followed. However, traditional design techniques to enable high performance microprocessors incur resource costs and typically suffer from poor energy efficiency. These overheads come at a considerable cost as most embedded designs are energy constrained and highly cost sensitive. The byproduct of these competing design constraints has been stagnating progress due to the ineffectiveness of traditional techniques. Through the use of this project's novel processor microarchitecture, commercial designs should observe approximately 30% greater energy efficiency and superior performance without incurring resource overhead. Applications such as networking and storage domains are initial candidates for adopting the design.This I-Corps project focuses on the creation of an energy-efficient microcontroller through the use of a novel processor microarchitecture. At the time most fundamental microprocessor techniques were developed, power was not a problem and transistors were scarce. To satisfy these constraints, designs focused on maximizing utilization of the few execution resources present. As transistors became more plentiful and performance of greater importance, designs utilized these additional transistors to enable complex organizational and scheduling techniques to maximize the operation of the scarce execution resources. This project's architecture reverses this trend by allocating additional transistors to execution resources and greatly simplifying organizational and scheduling overheads. Initial research suggests that considerable energy and area efficiency gains are possible while maintaining a high level of performance in comparison to current commercial designs. Additionally, the novel structure of this microprocessor enables many optimizations that are impractical in conventional designs due to their complex organization and scheduling.