RIA: Combined Logic Synthesis and Physical Design

这项研究致力于寻找有效的技术来同时和交互地产生逻辑综合和物理设计问题的解决方案。目前正在研究两个问题领域：将逻辑综合与物理设计相结合；以及布尔型网络的布局算法。在第一个领域，正在开发一个原型综合系统，该系统能够基于逻辑级别信息和关于互连线路和物理介质特性的详细数据来做出综合决策。其关键思想是生成布尔型网络的布局，该布尔型网络捕捉布局的结构。逻辑和布局表示之间的对应关系在迭代期间保持不变。既可以进行技术独立的逻辑转换，也可以进行技术依赖的逻辑转换。在第二个领域，正在研究如何分配I/O焊盘或放置未映射布尔网络的节点，其中节点仍具有独立于技术的逻辑实现。物理设计工具可以有效地捕捉布尔网络的结构特征，并且可以处理不精确或近似面积的节点、本征延迟和驱动。在逻辑综合和布图过程中，准确和高效的互连建模对算法的开发起着关键作用。

This research is on finding efficient techniques for producing solutions to logic synthesis and physical design problems both simultaneously and interactively. Two problem areas are being investigated: integrating logic synthesis with physical design; and layout algorithms for Boolean networks. In the first area, a prototype synthesis system which is capable of making synthesis decisions based on both logic level information and detailed data about the interconnecting wires and characteristics of the physical media is being developed. The key idea is to generate a placement of the Boolean network that captures the structure of the layout. The correspondence between logic and layout representations is maintained during iterations. Both technology independent and technology dependent logic transformations are accommodated. In the second area, ways to assign the I/O pads or place the nodes of an unmapped Boolean network, where the nodes still have technology independent logic realizations, are being investigated. Physical design tools which effectively capture the structural characteristics of Boolean networks and can handle nodes of inexact or approximate area, intrinsic delay and drive are being developed. Accurate and efficient modeling of interconnect during logic synthesis and layout plays a key role in the algorithm development.