RIA: Combined Logic Synthesis and Physical Design

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This research is on finding efficient techniques for producing solutions to logic synthesis and physical design problems both simultaneously and interactively. Two problem areas are being investigated: integrating logic synthesis with physical design; and layout algorithms for Boolean networks. In the first area, a prototype synthesis system which is capable of making synthesis decisions based on both logic level information and detailed data about the interconnecting wires and characteristics of the physical media is being developed. The key idea is to generate a placement of the Boolean network that captures the structure of the layout. The correspondence between logic and layout representations is maintained during iterations. Both technology independent and technology dependent logic transformations are accommodated. In the second area, ways to assign the I/O pads or place the nodes of an unmapped Boolean network, where the nodes still have technology independent logic realizations, are being investigated. Physical design tools which effectively capture the structural characteristics of Boolean networks and can handle nodes of inexact or approximate area, intrinsic delay and drive are being developed. Accurate and efficient modeling of interconnect during logic synthesis and layout plays a key role in the algorithm development.