SHF: Small: A Cross-Layer Modeling and Optimization Framework Targeting FinFET-based Designs Operating in Multiple Voltage Regimes

SHF：小型：跨层建模和优化框架，针对在多个电压范围内运行的基于 FinFET 的设计

• 批准号: 1423680
• 负责人: Massoud Pedram
• 金额: $ 43万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-09-01 至 2018-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1423680&HistoricalAwards=false
• 关键词: SHF; Small; Cross; Layer; Modeling

Recent studies emphasize the importance of energy-efficient computing for sustaining advancements in information technology and addressing critical societal challenges. The exploration of holistic power optimization and management solutions that cut across multiple layers of the computing stack and infrastructure to be studied in this project will better enable available opportunities for maximizing energy efficiency. The research will advance the state-of-the art in sub-10nm device design, modeling, and optimization, standard cell library design and characterization, circuit speed vs. energy efficiency vs. reliability trade space exploration, and heterogeneity modeling at the chip level. The challenges and opportunities in this research will provide directions for developing many of the technologies and approaches that are needed to design energy-efficient computing systems of the future and ensure sustainability of the information technology ecosystem. Education, outreach, and training programs enhanced by this project will include development of new educational modules, recruitment of minority and under-represented students, as well as undergraduate learning and research internship opportunities for undergraduates.From a technical standpoint, this project will innovate at two cross-layer boundaries: (i) Technology and Circuits, and (ii) Circuits and Architectures. More precisely, a first thrust of the research will focus on developing deeply-scaled (multi-gate) CMOS devices and logic cell libraries that offer high energy efficiency, fast switching speed, and reliability. A second thrust targets the design of low dynamic and standby power circuits, circuit designs capable of robust and energy-delay optimal operation in multiple voltage regimes, and means for effective chip-level power management. To accomplish these research objectives, analysis and simulation tools will be developed to characterize properties such as Ion/Ioff ratio, energy efficiency, and variation tolerance of the deeply-scaled (e.g., sub-10nm) FinFET devices. In addition, questions of how the new devices can be used for designing memory and logic cells that can seamlessly operate at low (near-threshold) and high (super-threshold) supply voltages will be explored. Finally, key challenges in modeling, deployment, and reconfiguration of circuit fabrics and architectural templates to improve the overall energy efficiency of system-on-chip designs will be addressed.

最近的研究强调了节能计算对于维持信息技术进步和应对关键社会挑战的重要性。本项目中要研究的跨计算堆栈和基础设施的多个层的整体电源优化和管理解决方案的探索将更好地实现最大限度地提高能源效率的机会。该研究将推进亚10纳米器件设计，建模和优化，标准单元库设计和表征，电路速度与能效与可靠性贸易空间探索以及芯片级异质性建模的最新技术。这项研究中的挑战和机遇将为开发许多设计未来节能计算系统所需的技术和方法提供方向，并确保信息技术生态系统的可持续性。通过该项目加强的教育、推广和培训计划将包括开发新的教育模块，招募少数民族和代表性不足的学生，以及为本科生提供本科学习和研究实习机会。从技术角度来看，该项目将在两个跨层边界进行创新：（i）技术和电路，（ii）电路和架构。更确切地说，研究的第一个重点将集中在开发深度缩放（多门）CMOS器件和逻辑单元库，提供高能效，快速开关速度和可靠性。第二个目标是低动态和待机功率电路的设计，电路设计能够在多个电压状态下进行鲁棒和能量延迟优化操作，以及有效的芯片级电源管理手段。为了实现这些研究目标，将开发分析和模拟工具来表征诸如Ion/Ioff比、能量效率和深度缩放（例如，sub-10 nm）FinFET器件。此外，新器件如何用于设计可以在低（近阈值）和高（超阈值）电源电压下无缝操作的存储器和逻辑单元的问题将被探讨。最后，将解决电路结构和架构模板的建模、部署和重新配置方面的关键挑战，以提高片上系统设计的整体能效。