SHF: Small: A Cross-Layer Modeling and Optimization Framework Targeting FinFET-based Designs Operating in Multiple Voltage Regimes

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Recent studies emphasize the importance of energy-efficient computing for sustaining advancements in information technology and addressing critical societal challenges. The exploration of holistic power optimization and management solutions that cut across multiple layers of the computing stack and infrastructure to be studied in this project will better enable available opportunities for maximizing energy efficiency. The research will advance the state-of-the art in sub-10nm device design, modeling, and optimization, standard cell library design and characterization, circuit speed vs. energy efficiency vs. reliability trade space exploration, and heterogeneity modeling at the chip level. The challenges and opportunities in this research will provide directions for developing many of the technologies and approaches that are needed to design energy-efficient computing systems of the future and ensure sustainability of the information technology ecosystem. Education, outreach, and training programs enhanced by this project will include development of new educational modules, recruitment of minority and under-represented students, as well as undergraduate learning and research internship opportunities for undergraduates.From a technical standpoint, this project will innovate at two cross-layer boundaries: (i) Technology and Circuits, and (ii) Circuits and Architectures. More precisely, a first thrust of the research will focus on developing deeply-scaled (multi-gate) CMOS devices and logic cell libraries that offer high energy efficiency, fast switching speed, and reliability. A second thrust targets the design of low dynamic and standby power circuits, circuit designs capable of robust and energy-delay optimal operation in multiple voltage regimes, and means for effective chip-level power management. To accomplish these research objectives, analysis and simulation tools will be developed to characterize properties such as Ion/Ioff ratio, energy efficiency, and variation tolerance of the deeply-scaled (e.g., sub-10nm) FinFET devices. In addition, questions of how the new devices can be used for designing memory and logic cells that can seamlessly operate at low (near-threshold) and high (super-threshold) supply voltages will be explored. Finally, key challenges in modeling, deployment, and reconfiguration of circuit fabrics and architectural templates to improve the overall energy efficiency of system-on-chip designs will be addressed.