NSF Workshop on Cross-Layer Power Optimization and Management

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This is a proposal to hold an NSF CISE-sponsored workshop in to survey the state-of-the art in cross-layer power optimization and management, to identify areas that require further research and development, and to chart a transformative research agenda for this field. The workshop is expected to bring together about 50 of the leading researchers studying system-wide power optimization techniques and dynamic power management from both academe and industry including representatives from major chip design companies. All of the material from the workshop will be made available to the research community and a detailed report will be prepared and submitted to NSF.Power efficiency is an important driver for the semiconductor industry and all of its components. By investigating the shortcomings and weaknesses of the current approaches to power and/or energy efficiency it is expected that a new slate of low power technology and circuit solutions with tangible impact on the design of the next generation portable electronics as well as high performance (yet energy aware) computing will be achieved.