System and Architectural Level Power Estimation, Optimization and Management

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This project investigates the problem of simultaneous scheduling and HW/SW mapping of the computational and communication processes in a generalized task flow graph so as to minimize the energy dissipation of the target system while satisfying a given deadline. This project also studies a number of problems related to power analysis and optimization at the behavioral and RT levels, including power modeling and characterization of Intellectual Property cores, and automatic clock gating. Finally, the project develops dynamic power management algorithms, which save power by shutting down idle devices or slowing down underutilized devices, and develops optimal policies for operating system (OS) directed power management and dynamic voltage and frequency scaling under a variety of system models