Presidential Faculty Fellows/Presidential Early Career Awards for Scientists and Engineers (PFF/PECASE): Power Estimation and Optimization in IC Design

这正在开发一种用于评估和/或预测CMOS电路的功耗的方法和有效技术。该方法的主要组成部分是调查抽样技术、基于自动机的序列压缩技术、行为/逻辑级别的协同仿真引擎、基于回归的功率宏建模技术和功率耗散的信息论模型。重点讨论了寄生电容估计、输入数据建模、存储层次和电路结构的影响，以及非线性延迟方程和定制线负载模型对估计器精度/效率的影响。与此同时，用于最小化VLSI电路和系统中的功耗的CAD方法和技术正在开发中。它们是：用于系统级分区和软硬件协同设计的低功耗优化技术和原型软件程序、通信综合、多电源电压调度、活动驱动寄存器分配和绑定、总线编码、用于交互有限状态机的状态分配、逻辑重构和简化、时序驱动布局、布线和零偏斜时钟树构造。最后，正在研究和自动化电源管理技术，例如(串行或并行)门控时钟、可停止时钟和电源模式之间的动态切换。

This is developing a methodology and efficient techniques for evaluating and/or predicting power dissipation of CMOS circuits. The major components of the proposed methodology are survey sampling techniques, automata-based sequence compaction techniques, a behavioral/logic level co-simulation engine, regression-based power macro-modeling techliques, and information-theoretic models of power dissipation. Special emphasis is being given to parasitic capacitance estimation, input data modeling, impact of memory hierarchy and circuit architecture, and effects of nonlinear delay equations and custom wire load models on accuracy/efficiency trade-offs of the estimators. Concurrently, CAD methodologies and techniques for minimizing the power dissipation in VLSI circuits and systems are being developed. These are: low power optimization techniques and prototype software programs for system-level partitioning and hardware/software codesign, communication synthesis, multiple supply voltage scheduling, activity-driven register allocation and binding, bus encoding, state assignment for interacting finite state machines, logic restructuring and simplification, timing-driven placement, routing and zero-skew clock tree construction. Finally, power management techniques such as (serial or parallel) gated clocks, stoppable clocks, and dynamic switching between power modes are being studied and automated.