Presidential Faculty Fellows/Presidential Early Career Awards for Scientists and Engineers (PFF/PECASE): Power Estimation and Optimization in IC Design

这是开发一种方法和有效的技术，用于评估和/或预测CMOS电路的功耗。所提出的方法的主要组成部分是调查抽样技术，基于自动机的序列压缩技术，行为/逻辑级协同仿真引擎，基于回归的功率宏观建模techliques，和功耗的信息理论模型。 特别强调的是寄生电容估计，输入数据建模，内存层次结构和电路架构的影响，以及非线性延迟方程和自定义线负载模型的估计器的精度/效率权衡的影响。同时，正在开发用于使VLSI电路和系统中的功率耗散最小化的CAD方法和技术。这些是：低功率优化技术和原型软件程序，用于系统级划分和硬件/软件协同设计、通信合成、多电源电压调度、活动驱动寄存器分配和绑定、总线编码、用于交互有限状态机的状态分配、逻辑重构和简化、定时驱动布局、路由和零偏斜时钟树构造。最后，电源管理技术，如（串行或并行）门控时钟，时钟和电源模式之间的动态切换正在研究和自动化。

This is developing a methodology and efficient techniques for evaluating and/or predicting power dissipation of CMOS circuits. The major components of the proposed methodology are survey sampling techniques, automata-based sequence compaction techniques, a behavioral/logic level co-simulation engine, regression-based power macro-modeling techliques, and information-theoretic models of power dissipation. Special emphasis is being given to parasitic capacitance estimation, input data modeling, impact of memory hierarchy and circuit architecture, and effects of nonlinear delay equations and custom wire load models on accuracy/efficiency trade-offs of the estimators. Concurrently, CAD methodologies and techniques for minimizing the power dissipation in VLSI circuits and systems are being developed. These are: low power optimization techniques and prototype software programs for system-level partitioning and hardware/software codesign, communication synthesis, multiple supply voltage scheduling, activity-driven register allocation and binding, bus encoding, state assignment for interacting finite state machines, logic restructuring and simplification, timing-driven placement, routing and zero-skew clock tree construction. Finally, power management techniques such as (serial or parallel) gated clocks, stoppable clocks, and dynamic switching between power modes are being studied and automated.