Analysis and Digital Techniques for Battery-Powered Digital CMOS Circuits

点击翻译按钮获取中文摘要

The research project is on power modeling, analysis and minimization for battery-powered digital CMOS circuits. An integrated battery-hardware model of the battery-operated circuits is being developed. It accounts for architectural and gate-level features of the circuit, statistical properties of the instructions and data that are applied to the circuit, and electro-chemical and output characteristics of the battery cell that powers the circuit. Using this unified model, the project is addressing the problem of finding appropriate metrics and effective design practices to maximize the battery service life under a performance constraint. Algorithms and techniques are being developed for: (1) static and dynamic voltage scaling, selection of battery cells to match a given circuit, (2) RT-level design of low power VLSI circuits to match a given battery cell, (3) use of multiple battery cell types within a battery pack to maximize the battery service life for given form factor and weight, and (4) dynamic power management. Powerful mathematical models and algorithms for power estimation and management in complex battery-powered digital CMOS designs are being explored.