High-Quality Tests for Combinational Circuits

本研究旨在寻找一种程序，以推导出紧凑或小型的测试集，这些测试集涵盖了一组全面的建模故障，这是实现制造的VLSI芯片高可靠性所必需的。一个允许各种故障模型统一表示的故障模型正在被探索，作为生成小而全面的测试集的基础。一套工具，以处理不同方面的测试质量的组合和全扫描顺序电路正在建立。它们是：1；针对综合故障集生成小测试集，包括有效处理路径延迟故障；2. 可测试性设计，允许在修改后的电路中检测到原始电路中无法检测到的故障；和3。基于无法使用存储模式测试时生成的测试集生成内建测试模式。

Pomeranz This research is on finding procedures to derive compact or small test sets that cover a comprehensive set of modeled faults, required to achieve high reliability of manufactured VLSI chips. A fault model that allows uniform representation of various fault models is being explored as the basis for generating small, yet comprehensive test sets. A set of tools to deal with different aspects of testing quality for combinational and fully scanned sequential circuits is being built. These are: 1. generation of small test sets for a comprehensive set of faults, including efficient treatment of path delay faults; 2. design for testability to allow faults undetectable in the original to be detected in a modified circuit; and 3. built in test pattern generation based on the test sets produced when stored pattern tests cannot be used.