High-Quality Tests for Combinational Circuits

波美兰兹这项研究的目的是寻找一种程序，以获得紧凑或小型的测试集，以覆盖全面的建模故障集，这是实现所制造的VLSI芯片的高可靠性所必需的。正在探索一种允许统一表示各种故障模型的故障模型，以此作为生成小而全面的测试集的基础。正在建立一套工具来处理组合和完全扫描时序电路的测试质量的不同方面。这些是：1.为包括路径延迟故障的有效处理在内的综合故障集生成小测试集；2.可测试性设计，以允许在修改后的电路中检测原始电路中无法检测到的故障；以及3.基于当不能使用存储的模式测试时产生的测试集来生成内置测试模式。

Pomeranz This research is on finding procedures to derive compact or small test sets that cover a comprehensive set of modeled faults, required to achieve high reliability of manufactured VLSI chips. A fault model that allows uniform representation of various fault models is being explored as the basis for generating small, yet comprehensive test sets. A set of tools to deal with different aspects of testing quality for combinational and fully scanned sequential circuits is being built. These are: 1. generation of small test sets for a comprehensive set of faults, including efficient treatment of path delay faults; 2. design for testability to allow faults undetectable in the original to be detected in a modified circuit; and 3. built in test pattern generation based on the test sets produced when stored pattern tests cannot be used.