RIA: Test Generation for Synchronous Sequential Circuits

这项研究是在完全故障覆盖（在低成本）， 同步时序电路 一种测试生成策略， 说明了现有测试生成过程的局限性 正在接受调查 该方法的本质在于 多时间观测假设，这消除了 通过观察电路的响应来检测故障 在一个单一的时间单位。 建立了由单一断层和 多个转换故障，其中包括许多门级卡在 缺点，正在探索中。 测试生成过程的目的是 在中型和大型电路中，称为互连 冲锋枪 这种电路的分解算法是 正在调查 正在设计一套全面的工具 特别是为了实现完全故障覆盖的目的。 这些工具包括：测试生成、仿真、抽取和 分解程序。

This research is on complete fault coverage (at low cost) for synchronous sequential circuits. A test generation strategy, which alleviates the limitations of existing test generation procedures is being investigated. The essence of the approach is in the multiple time observation assumption, which removes the requirement that a fault be detected by observation of the circuit's response at a single time unit. A fault model comprised of single and multiple transition faults, which covers many gate level stuck at faults, is being explored. Test generation procedures are aimed at medium sized and large circuits, described as interconnections of submachines. Algorithms for decomposition of such circuits are being investigated. A comprehensive set of tools is being designed especially for the purpose of achieving complete fault coverage. The tools include: test generation, simulation, extraction and decomposition procedures.