RIA: Test Generation for Synchronous Sequential Circuits

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This research is on complete fault coverage (at low cost) for synchronous sequential circuits. A test generation strategy, which alleviates the limitations of existing test generation procedures is being investigated. The essence of the approach is in the multiple time observation assumption, which removes the requirement that a fault be detected by observation of the circuit's response at a single time unit. A fault model comprised of single and multiple transition faults, which covers many gate level stuck at faults, is being explored. Test generation procedures are aimed at medium sized and large circuits, described as interconnections of submachines. Algorithms for decomposition of such circuits are being investigated. A comprehensive set of tools is being designed especially for the purpose of achieving complete fault coverage. The tools include: test generation, simulation, extraction and decomposition procedures.