Cache Architectures for Large Shared Memory Multiprocessors

Bhuyan 这个项目解决的问题，设计一致的高速缓存可扩展的多处理器共享地址空间。 由于互连网络中缺乏足够的广播容量，在大规模系统中保持缓存一致性是耗时的。 一个动态的高速缓存一致性协议正在设计和评估，以减少大型系统中的该高速缓存一致性开销。 该协议将无效或更新流量限制在互连网络的子树中。 该项目的第一阶段包括将根树嵌入到各种网络中，并使用嵌入研究目录的硬件和时序复杂性。 在第二阶段，诸如容错自适应路由和任务映射等问题正在得到解决。 研究采用了分析技术和执行驱动的模拟。

Bhuyan This project addresses the problem of designing coherent caches for scalable multiprocessors with shared address spaces. Maintaining cache coherence in large-scale systems is time consuming due to the lack of sufficient broadcasting capacity in the interconnection networks. A dynamic cache coherence protocol is being designed and evaluated to reduce the cache coherence overheads in large systems. This protocol limits invalidation or update traffic to a subtree of the interconnection network. The first phase of the project consists of embedding rooted trees into various networks, and studying the hardware and timing complexities of directories using the embeddings. In a second phase, issues such as fault tolerance adaptive routing, and task mapping are being addressed. The research makes use of analytic techniques and execution driven simulation.