Scheduling in High-Performance Internet Routers

随着互联网的发展，对路由器带宽和服务质量的要求呈指数级增长。目前的路由器采用输入排队交叉开关，需要复杂的调度技术的数据包传输。在这个项目中，新的基于数据包的调度算法的开发和测试高性能的互联网路由器操作。公平调度算法也被合并在交叉开关中，以分配与分组的请求预留成比例的带宽。基于流和基于端口的公平调度算法的设计类似于赤字轮循技术。为了将这些路由器扩展到太比特带宽，还基于可扩展网络开发了全连接交叉开关和路由器拓扑的架构。这些网络的调度和路由算法进行了调查。所提出的研究的内在优点在于在不同的IP路由器的交换机组织，执行最佳的互联网流量的新的调度技术的发展。通过网络仿真和硬件实验对算法进行了验证。一个跟踪驱动的可配置的仿真测试床的开发，公开可用的互联网跟踪可以作为输入工作量。交叉开关和调度算法的硬件实现使用现场可编程门阵列（FPGA）和SRAM。这样的实现产生所提出的算法和它们的硬件复杂性的准确分析。这项工作的更广泛的影响是显而易见的，通过高质量的出版物，工业合作，并通过这个项目资助的学生教育。

Scheduling in High-Performance Internet RoutersAbstractAs the Internet expands, the demand on routers for more bandwidth and better quality of service (QoS) increases exponentially. Current routers employ input-queued crossbar switches that require sophisticated scheduling techniques for packet transmission. In this project, new packet-based scheduling algorithms are developed and tested for high-performance Internet router operation. Fair scheduling algorithms are also incorporated in the crossbar to allocate bandwidths proportional to the request reservations of the packets. Both flow-based and port-based fair scheduling algorithms are designed similar to the deficit round-robin technique. To scale these routers to terabit bandwidth, architectures for fully connected crossbar switches and router topologies are also developed based on scalable networks. Scheduling and routing algorithms for these networks are investigated.The intrinsic merit of the proposed research lies in the development of new scheduling techniques for different switch organizations of an IP router that perform optimally for the Internet traffic. The algorithms are tested both through network simulation and hardware experiments. A trace-driven configurable simulation test-bed is developed, where publicly available Internet traces can be fed as the input workload. The crossbar switch and scheduling algorithms are implemented in hardware using field programmable gate arrays (FPGAs) and SRAMs. Such an implementation produces an accurate analysis of the proposed algorithms and their hardware complexities. The broader impact of the work is evident through quality publication, industrial collaboration, and student education funded through this project.