Research on Circuit Partitioning

该项目是对新一代分层划分方法的研究，目的是1)处理高电路复杂性，2)在I/O管脚数限制下改善系统性能，3)控制模块间延迟以优化系统性能。主要研究人员建议通过采用不同的电路模型(包括Petri网、数据流和状态机)、通过提高方法的效率和有效性以及通过推导关于分区公式变化的理论结果来扩展先前的分区研究。他计划将分区方法应用到各种硬件仿真机器的网表映射中，并找到这些方法在VLSI设计问题上的潜在应用

This project is an investigation into a new generation of hierarchical partitioning methods motivated by the need to 1) cope with high circuit complexity, 2) improve a system's performance under I/O pin count constraints, and 3) control intermodule delay in order to optimize system performance. The principal investigator proposes to extend previous partitioning research by adopting different circuit models including petri nets, data flows, and state machines, by improving the efficiency and effectiveness of the methods, and by deriving theoretical results on variations of partitioning formulations. He plans to apply partitioning methods to netlist mappings for various hardware emulation machines and to find potential applications of these methods to VLSI design problems