Hybrid Clock Networks using Distortionless Transmission Lines

使用无失真传输线的混合时钟网络

• 批准号: 0618163
• 负责人: Chung-Kuan Cheng
• 金额: $ 7.5万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-08-15 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0618163&HistoricalAwards=false
• 关键词: Hybrid; Clock; Networks; using; Distortionless

Abstract0618163PI: Chung-Kuan ChengCSE Dept., UC, San DiegoTitle: Hybrid Clock Networks Using Distortionless Transmission LinesWith the advance of the VLSI technology, the variation of interconnect delay is becoming critical since interconnect delay plays a dominant role in system performance. Process, voltage, and temperature variations can have significant effects on interconnect delay. Therefore, the robustness of interconnect design is important. This is especially crucial for clock distributions because the delay variations contribute to clock jitters and skews.In a recent invention, Cheng's group devised a distortionless transmission line which achieves the speed of light at an 85% or greater reduction in power consumption over traditional wires. The proposed project explores the utilization of the distortionless transmission line integrated with the interconnect topologies, circuit styles, and electromagnetic wave techniques into a hybrid network. The exploration can lead to the design of the speed of light, extremely low power, and low jitter clock distributions. The SGER is the best means for this exploratory and high return project because of the availability of the funding in a timely manner.

Abstract0618163PI：Chung-Kuan Chengcse Dept。，UC，San DieGotitle：使用无失真输电线路的混合时钟网络随着VLSI技术的发展，互连延迟的进步变得至关重要，因为互连延迟在系统性能中起主要作用。过程，电压和温度变化可能会对互连延迟产生重大影响。因此，互连设计的鲁棒性很重要。这对于时钟分布尤为重要，因为延迟变化有助于时钟的抖动并偏斜。在最近的发明中，郑的小组设计了一条无失真的传输线，该线路以85％或更高的降低传统电线，以85％或更高的速度达到了光速。拟议的项目探讨了与互连拓扑，电路样式和电磁波技术集成到混合网络中的无失真传输线的利用。探索可以导致设计速度，极低功率和低抖动时钟分布的设计。由于及时获得资金，SGER是该探索性和高回报项目的最佳手段。