Hybrid Clock Networks using Distortionless Transmission Lines

使用无失真传输线的混合时钟网络

• 批准号: 0618163
• 负责人: Chung-Kuan Cheng
• 金额: $ 7.5万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-08-15 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0618163&HistoricalAwards=false
• 关键词: Hybrid; Clock; Networks; using; Distortionless

Abstract0618163PI: Chung-Kuan ChengCSE Dept., UC, San DiegoTitle: Hybrid Clock Networks Using Distortionless Transmission LinesWith the advance of the VLSI technology, the variation of interconnect delay is becoming critical since interconnect delay plays a dominant role in system performance. Process, voltage, and temperature variations can have significant effects on interconnect delay. Therefore, the robustness of interconnect design is important. This is especially crucial for clock distributions because the delay variations contribute to clock jitters and skews.In a recent invention, Cheng's group devised a distortionless transmission line which achieves the speed of light at an 85% or greater reduction in power consumption over traditional wires. The proposed project explores the utilization of the distortionless transmission line integrated with the interconnect topologies, circuit styles, and electromagnetic wave techniques into a hybrid network. The exploration can lead to the design of the speed of light, extremely low power, and low jitter clock distributions. The SGER is the best means for this exploratory and high return project because of the availability of the funding in a timely manner.

摘要[0618163]UC， San diego . tle：采用无失真传输线的混合时钟网络随着VLSI技术的发展，互连延迟的变化变得越来越重要，因为互连延迟在系统性能中起着主导作用。工艺、电压和温度变化会对互连延迟产生显著影响。因此，互连设计的鲁棒性非常重要。这对于时钟分布尤其重要，因为延迟变化会导致时钟抖动和倾斜。在最近的一项发明中，Cheng的团队设计了一种无扭曲的传输线，它在达到光速的同时，比传统电线的功耗降低了85%或更多。本计画探索将无失真传输线与互连拓扑、电路样式及电磁波技术整合成混合网路。这种探索可以导致设计出光速、极低功耗和低抖动时钟分布。SGER是这一探索性高回报项目的最佳手段，因为它可以及时获得资金。