SHF: Small: Research on Standard Cell Layout to Facilitate the VLSI Technology Scaling

SHF：小型：研究标准单元布局以促进 VLSI 技术扩展

• 批准号: 2110419
• 负责人: Chung-Kuan Cheng
• 金额: $ 54.79万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2021
• 资助国家: 美国
• 起止时间: 2021-10-01 至 2024-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2110419&HistoricalAwards=false
• 关键词: SHF; Small; Research; Standard; Cell

Physical layout plays an essential role in the scaling of VLSI technology nodes. As the whole VLSI industry tries to sustain technology scaling, the paradigm is shifting from geometric scaling to design technology co-optimization, and soon to system technology co-optimization. The paradigm shifts require the advancement of physical-layout techniques to tackle the new problems related to sustaining the scaling of the technology. The project works on the advancement of standard cell layout in terms of analysis, synthesis, and optimization to embrace the demand of the design technology and system technology co-optimization. The objectives are to facilitate the scaling of VLSI technology nodes. The approach is to perform system and design co-optimization in the domain of physical layout. The outcome would benefit the whole VLSI ecosystem including consumers, markets, and research and development. The project is facilitating the advising of a diverse group of graduate and undergraduate students including minority, female students, and students under adverse circumstances.The research of technology scaling is focusing on four thrusts. (1) Routing analysis and unrouteable case diagnosis: The study analyzes the VLSI routeability and diagnoses the cause of the unrouteable cases to embrace the increasing complexity of the conditional design rules. (2) Library cell layout synthesis: The research automates the library standard cell layout to facilitate the technology scaling. (3) Design and system technology co-optimization with pitch scaling: The research facilitates design and system technology co-optimization with pitch scaling. (4) Extension of CMOS technologies and beyond: The exploration studies 3D devices, new materials, and novel architectures. The project outcomes include advanced methodology, theory, and algorithms for VLSI physical layout, and software packages for a suite of layout tools. The results are being disseminated for VLSI production via collaboration with research laboratories and technology companies.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

物理布局在VLSI技术节点的缩放中起着至关重要的作用。随着整个VLSI行业试图维持技术规模，范式正在从几何扩展到设计技术合作，并很快到系统技术合作。范式转移需要进步的物理层压技术，以解决与维持技术缩放有关的新问题。该项目在分析，合成和优化方面致力于提高标准单元格的发展，以包含设计技术和系统技术合作的需求。这些目标是促进VLSI技术节点的缩放。该方法是在物理布局的域中执行系统和设计合作式化。结果将使包括消费者，市场以及研发在内的整个VLSI生态系统受益。该项目正在促进在不利情况下包括少数群体，女学生和学生在内的一群研究生和本科生的建议。技术规模的研究集中在四个推力上。 （1）路由分析和不符合案例诊断：研究分析了VLSI的路由性，并诊断出不受欢迎的病例的原因，以接受条件设计规则的日益复杂性。 （2）库单元格布局综合：研究自动化库标准单元格的布局以促进技术扩展。 （3）与音高缩放的设计和系统技术合作化：研究促进了设计和系统技术与俯仰缩放的合作优化。 （4）CMOS技术及以后的扩展：勘探研究3D设备，新材料和新型体系结构。该项目的结果包括VLSI物理布局的高级方法论，理论和算法，以及一套布局工具的软件包。该结果通过与研究实验室和技术公司的合作进行了VLSI生产的传播。该奖项反映了NSF的法定任务，并被认为是值得通过基金会的知识分子优点和更广泛的影响审查标准通过评估来支持的。

项目成果

Assessment of Reinforcement Learning for Macro Placement

强化学习对宏观布局的评估

• DOI: 10.1145/3569052.3578926
• 发表时间: 2023
• 期刊: Proceedings of the 2023 International Symposium on Physical Design
• 作者: Cheng, Chung-Kuan;Kahng, Andrew B.;Kundu, Sayak;Wang, Yucheng;Wang, Zhiang
• 通讯作者: Wang, Zhiang

Placement Initialization via Sequential Subspace Optimization with Sphere Constraints

通过具有球体约束的顺序子空间优化进行布局初始化

• DOI: 10.1145/3569052.3571877
• 发表时间: 2023
• 期刊: ACM/IEEE ISPD 2023
• 作者: Chen, Pengwen;Cheng, Chung-Kuan;Chern, Albert;Holtz, Chester;Li, Aoxi;Wang, Yucheng
• 通讯作者: Wang, Yucheng

Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis

设计和系统技术协同优化的机器学习预测灵敏度分析

• DOI: 10.1109/tvlsi.2022.3172938
• 发表时间: 2022
• 期刊: IEEE Transactions on Very Large Scale Integration (VLSI
• 作者: Cheng, Chung-Kuan;Ho, Chia-Tung;Holtz, Chester;Lee, Daeyeal;Lin, Bill
• 通讯作者: Lin, Bill

Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization

通过利润最大化实现面向净分离的印刷电路板布局

• DOI: 10.1109/asp-dac52403.2022.9712480
• 发表时间: 2022
• 期刊: 2022 27th ASP Design Automation Conference
• 作者: Cheng, Chung-Kuan;Ho, Chia-Tung;Holtz, Chester
• 通讯作者: Holtz, Chester

Monolithic 3D semiconductor footprint scaling exploration based on VFET standard cell layout methodology, design flow, and EDA platform

基于 VFET 标准单元布局方法、设计流程和 EDA 平台的单片 3D 半导体封装扩展探索

• 发表时间: 2022
• 期刊: IEEE access
• 影响因子: 3.9
• 作者: Cheng, Chung-Kuan;Ho, Chia-Tung;Lee, Daeyeal;Lin, Bill
• 通讯作者: Lin, Bill