SHF: Small: Research on Standard Cell Layout to Facilitate the VLSI Technology Scaling

物理布局在超大规模集成电路工艺节点的规模化中起着至关重要的作用。随着整个超大规模集成电路行业试图维持技术规模化，范式正在从几何规模化转向设计技术协同优化，并很快转向系统技术协同优化。这种范式转变需要物理布局技术的进步，以解决与维持技术规模相关的新问题。本项目致力于标准单元布局的分析、综合和优化，以满足设计技术和系统技术协同优化的需求。其目标是促进超大规模集成电路技术节点的扩展。该方法是执行系统和设计协同优化的物理布局的域。其结果将有利于整个VLSI生态系统，包括消费者、市场和研发。该项目旨在为包括少数民族学生、女生和处境不利的学生在内的各种研究生和本科生群体提供咨询服务。技术规模化的研究主要集中在四个方面。(1)路由分析和不可路由的情况下诊断：该研究分析了超大规模集成电路的可路由性和诊断的原因不可路由的情况下，拥抱条件设计规则的复杂性不断增加。(2)库单元布局综合：该研究使库标准单元布局自动化，以促进技术扩展。(3)设计和系统技术协同优化与间距缩放：该研究促进了设计和系统技术协同优化与间距缩放。(4)CMOS技术的扩展及其他：探索研究3D器件，新材料和新架构。该项目的成果包括先进的方法，理论和算法的超大规模集成电路的物理布局，和软件包的一套布局工具。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Physical layout plays an essential role in the scaling of VLSI technology nodes. As the whole VLSI industry tries to sustain technology scaling, the paradigm is shifting from geometric scaling to design technology co-optimization, and soon to system technology co-optimization. The paradigm shifts require the advancement of physical-layout techniques to tackle the new problems related to sustaining the scaling of the technology. The project works on the advancement of standard cell layout in terms of analysis, synthesis, and optimization to embrace the demand of the design technology and system technology co-optimization. The objectives are to facilitate the scaling of VLSI technology nodes. The approach is to perform system and design co-optimization in the domain of physical layout. The outcome would benefit the whole VLSI ecosystem including consumers, markets, and research and development. The project is facilitating the advising of a diverse group of graduate and undergraduate students including minority, female students, and students under adverse circumstances.The research of technology scaling is focusing on four thrusts. (1) Routing analysis and unrouteable case diagnosis: The study analyzes the VLSI routeability and diagnoses the cause of the unrouteable cases to embrace the increasing complexity of the conditional design rules. (2) Library cell layout synthesis: The research automates the library standard cell layout to facilitate the technology scaling. (3) Design and system technology co-optimization with pitch scaling: The research facilitates design and system technology co-optimization with pitch scaling. (4) Extension of CMOS technologies and beyond: The exploration studies 3D devices, new materials, and novel architectures. The project outcomes include advanced methodology, theory, and algorithms for VLSI physical layout, and software packages for a suite of layout tools. The results are being disseminated for VLSI production via collaboration with research laboratories and technology companies.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.