RIA: Research on Partitioning for High Speed and High Density Circuit Design

本研究是针对高速高密度电路设计的性能驱动分割。将电路从系统级划分到基本布局模块的自动划分系统的工具正在开发中。对于有几百万门的系统，使用一种称为比率切割的技术来定义系统的层次结构。比值切割用于识别聚类结构，从而将系统组织成树状结构。探索了一种启发式比例切割算法，用于设计的分层划分。一旦创建了分区，就会出现优化问题。人们正在研究使用神经网络、特殊图上的划分和其他方法来解决这个问题。

This research is on performance driven partitioning for high speed and high density circuit design. Tools for an automatic partitioning system which divides circuits from the system level to basic layout modules are being developed. For systems of several million gates, a technique, called the ratio cut, is used to define the hierarchy of the system. The ratio cut is used to identify the cluster structure and thus organize the system into a tree structure. A heuristic ratio cut algorithm is being explored for use in hierarchal partitioning of the design. Once a partition has been made there is an optimization problem. Solutions to this problem are being investigated using neural nets, partitioning on special graphs and other methods.