RIA: Research on Partitioning for High Speed and High Density Circuit Design

RIA：高速高密度电路设计分区研究

• 批准号: 9009260
• 负责人: Chung-Kuan Cheng
• 金额: $ 6.8万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-07-01 至 1992-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9009260&HistoricalAwards=false
• 关键词: RIA; Research; Partitioning; Speed; Density

This research is on performance driven partitioning for high speed and high density circuit design. Tools for an automatic partitioning system which divides circuits from the system level to basic layout modules are being developed. For systems of several million gates, a technique, called the ratio cut, is used to define the hierarchy of the system. The ratio cut is used to identify the cluster structure and thus organize the system into a tree structure. A heuristic ratio cut algorithm is being explored for use in hierarchal partitioning of the design. Once a partition has been made there is an optimization problem. Solutions to this problem are being investigated using neural nets, partitioning on special graphs and other methods.

这项研究是针对高速和高密度电路设计的性能驱动分区的。 正在开发将电路从系统级别划分为基本布局模块的自动分区系统的工具。 对于数百万门的系统，一种称为削减比例的技术用于定义系统的层次结构。 比率切割用于识别群集结构，从而将系统组织到树结构中。 正在探索一种启发式比率削减算法，以用于设计层次分区。 一旦进行了分区，就有一个优化问题。 该问题的解决方案正在使用神经网，在特殊图和其他方法上进行分配。