RIA: Research on Partitioning for High Speed and High Density Circuit Design

RIA：高速高密度电路设计分区研究

• 批准号: 9009260
• 负责人: Chung-Kuan Cheng
• 金额: $ 6.8万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-07-01 至 1992-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9009260&HistoricalAwards=false
• 关键词: RIA; Research; Partitioning; Speed; Density

This research is on performance driven partitioning for high speed and high density circuit design. Tools for an automatic partitioning system which divides circuits from the system level to basic layout modules are being developed. For systems of several million gates, a technique, called the ratio cut, is used to define the hierarchy of the system. The ratio cut is used to identify the cluster structure and thus organize the system into a tree structure. A heuristic ratio cut algorithm is being explored for use in hierarchal partitioning of the design. Once a partition has been made there is an optimization problem. Solutions to this problem are being investigated using neural nets, partitioning on special graphs and other methods.

本研究是关于性能驱动的分区， 高密度电路设计。 用于自动分区系统的工具 它将电路从系统级划分为基本布局模块， 正在开发中。 对于几百万门的系统，一种技术， 称为比率切割，用于定义系统的层次结构。 比率切割用于识别簇结构， 将系统组织成树形结构。 启发式比率削减 算法正在探索用于分层分区的 设计 一旦分区已经作出有一个优化 问题. 这个问题的解决方案正在研究使用神经网络 网、特殊图上的划分等方法。