Research on Interconnect-Dominated Floorplanning

该项目研究互联为主的平面规划。平面图组织了电线的拓扑结构和缓冲区的分配，而布置和布线则作为支持工具来满足设计要求。该项目包括以下方面的探索。技术总体规划：给定一个电路设计项目，技术总体规划确定在成本和性能方面提供最佳互连能力的技术。采用分层设计框架的逻辑布局：逻辑布局利用了设计层次，并推导出互连延迟的影响。物理布局平面图：物理布局平面图是支持互连优化操作的基础。

The project researches interconnect-dominated floorplanning. The floorplanning organizes the topology of wires and the assignment of buffers while placement and routing are structured as supporting tools to fulfill the design requirements. The project includes exploration of the following. Technology Floorplanning: Given a circuit design project, the technology floorplanning identifies the technology that provides the best interconnect capability in terms of cost and performance. Logic Floorplanning with a Hierarchical Design Framework: A logic floorplanning takes advantage of the design hierarchy and derives the effect of interconnect delay. Physical Layout Floorplanning: Physical layout floorplanning serves as a foundation to support the interconnect optimization operations.