Research on Interconnect-Dominated Floorplanning

互连主导的布局规划研究

• 批准号: 9987678
• 负责人: Chung-Kuan Cheng
• 金额: $ 40.09万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-08-01 至 2004-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9987678&HistoricalAwards=false
• 关键词: Research; Interconnect; Dominated; Floorplanning

The project researches interconnect-dominated floorplanning. The floorplanning organizes the topology of wires and the assignment of buffers while placement and routing are structured as supporting tools to fulfill the design requirements. The project includes exploration of the following. Technology Floorplanning: Given a circuit design project, the technology floorplanning identifies the technology that provides the best interconnect capability in terms of cost and performance. Logic Floorplanning with a Hierarchical Design Framework: A logic floorplanning takes advantage of the design hierarchy and derives the effect of interconnect delay. Physical Layout Floorplanning: Physical layout floorplanning serves as a foundation to support the interconnect optimization operations.

该项目研究了以互连为主导的平面图。平面图组织电线的拓扑结构和缓冲区的分配，而放置和路由则是满足设计要求的支持工具。该项目包括以下探索。技术平面图：鉴于电路设计项目，技术平面图确定了在成本和性能方面提供最佳互连功能的技术。使用层次设计框架进行逻辑平面图：逻辑平面图利用了设计层次结构，并导致了互连延迟的效果。物理布局平面图：物理布局地板平面图是支持互连优化操作的基础。