SHF: Small: VLSI Circuit Simulation Using Parallel Processing

SHF：小型：使用并行处理的 VLSI 电路仿真

• 批准号: 1017864
• 负责人: Chung-Kuan Cheng
• 金额: $ 45万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1017864&HistoricalAwards=false
• 关键词: SHF; Small; VLSI; Circuit; Simulation

The objective of this research is to analyze and verify VLSI systems and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits. The intellectual merit of this proposal lies in the algorithm and software package for full chip simulation. Circuit simulation is one of the main bottlenecks in VLSI design in industry. The complexity of full chip simulations chip is prohibitive for state-of-the-art designs. The project could significantly improve the turnaround time and capacity of whole circuit simulations, enabling the VLSI industry to be more competitive during a time of technological disruption and hence rapid design evolution. The run time software techniques developed by the investigation should apply to a wide range of applications beyond the simulator that could benefit from latency tolerant formulation. New platforms that employ hardware acceleration, e.g. GPUs, will also benefit, since they place a premium on communication.The broader impacts include the following educational and outreach components. (1) The research will be conducted in collaboration with electronic design automation companies and design houses and the findings will be directly transferred to industry for 3D IC designs. (2) Seminars and new courses will be offered to educate undergraduate and graduate students. A new graduate-level course on circuit simulation using parallel processing will be developed and taught at UCSD as well as at industrial partner sites. (3) Advanced technology books and class handouts will be released through publishers and web-sites. For wider educational outreach, webinars will be presented. (4) The research team is highly integrated and consists of two investigators and a senior researcher from different backgrounds at UCSD and Lawrence Berkeley National Research Laboratory. Education of graduate students involved in the project will be enhanced by participation in an interdisciplinary collaborative research. To disseminate our excitement with the ideas outlined here, and to stimulate the scientific imagination of future scientists, the team will give demonstrations and lectures for minority and disadvantaged students.

这项研究的目的是分析和验证超大规模集成电路系统，并证明大大提高了可扩展性，以提高预测电路建模的质量和范围。由于先进制造技术的互连优势，VLSI电路模拟变得至关重要。功能模块通过基板集成，并通过具有寄生效应的导线连接。整个系统的仿真将使设计人员能够充分掌握电路的瞬态行为。这个建议的智力价值在于全芯片仿真的算法和软件包。电路仿真是工业上超大规模集成电路设计的主要瓶颈之一。全芯片仿真的复杂性使最先进的设计望而却步。该项目可以显着提高整个电路仿真的周转时间和容量，使VLSI行业在技术中断和快速设计演变的时期更具竞争力。调查开发的运行时软件技术应适用于广泛的应用程序以外的模拟器，可以受益于延迟容忍制定。采用硬件加速的新平台（如GPU）也将受益，因为它们重视通信。更广泛的影响包括以下教育和推广组件。(1)该研究将与电子设计自动化公司和设计公司合作进行，研究结果将直接转移到3D IC设计行业。(2)将提供研讨会和新课程，以教育本科生和研究生。一个新的研究生水平的课程电路模拟使用并行处理将开发和教UCSD以及在工业合作伙伴网站。(3)先进的技术书籍和课堂讲义将通过出版商和网站发布。为了更广泛的教育推广，将举办网络研讨会。(4)该研究团队高度整合，由来自UCSD和劳伦斯伯克利国家研究实验室不同背景的两名研究人员和一名高级研究员组成。参与该项目的研究生的教育将通过参与跨学科的合作研究得到加强。为了传播我们对这里概述的想法的兴奋，并激发未来科学家的科学想象力，该团队将为少数民族和弱势学生提供演示和讲座。