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SHF: Small: VLSI Circuit Simulation Using Parallel Processing

SHF: Small: VLSI Circuit Simulation Using Parallel Processing
SHF:小型:使用并行处理的 VLSI 电路仿真
批准号:
1017864
负责人:
Chung-Kuan Cheng
金额:
$45.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2010
资助国家:
美国
项目状态:
已结题
起止时间:
2010-09-01 至 2015-08-31

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中文摘要
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英文摘要
The objective of this research is to analyze and verify VLSI systems and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits. The intellectual merit of this proposal lies in the algorithm and software package for full chip simulation. Circuit simulation is one of the main bottlenecks in VLSI design in industry. The complexity of full chip simulations chip is prohibitive for state-of-the-art designs. The project could significantly improve the turnaround time and capacity of whole circuit simulations, enabling the VLSI industry to be more competitive during a time of technological disruption and hence rapid design evolution. The run time software techniques developed by the investigation should apply to a wide range of applications beyond the simulator that could benefit from latency tolerant formulation. New platforms that employ hardware acceleration, e.g. GPUs, will also benefit, since they place a premium on communication.The broader impacts include the following educational and outreach components. (1) The research will be conducted in collaboration with electronic design automation companies and design houses and the findings will be directly transferred to industry for 3D IC designs. (2) Seminars and new courses will be offered to educate undergraduate and graduate students. A new graduate-level course on circuit simulation using parallel processing will be developed and taught at UCSD as well as at industrial partner sites. (3) Advanced technology books and class handouts will be released through publishers and web-sites. For wider educational outreach, webinars will be presented. (4) The research team is highly integrated and consists of two investigators and a senior researcher from different backgrounds at UCSD and Lawrence Berkeley National Research Laboratory. Education of graduate students involved in the project will be enhanced by participation in an interdisciplinary collaborative research. To disseminate our excitement with the ideas outlined here, and to stimulate the scientific imagination of future scientists, the team will give demonstrations and lectures for minority and disadvantaged students.
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