Electrode Topography in Plasma Processing Reactors: Uniformity, Dust Particle Trapping and Differential Wafer Charging

半导体工业协会（SIA）已经设定了目标，到2001年，在微电子器件中实现全行业的0.18微米特征尺寸，晶片尺寸大到40厘米。 这些目标非常严格，并且离子和自由基流到表面的均匀性的公差由它们产生的均匀性和将它们驱动到衬底的电势梯度或流场的均匀性决定。 这些通量和梯度对扰动等离子体的电极形貌高度敏感。电极形貌的示例是晶片本身、从晶片保持器螺栓孔突出的夹子、以及在其他光滑表面上的电极材料中的不连续性。 等离子体特性甚至会受到放置在晶片下的金属或金属片的影响。 研究人员建议执行一个计算机建模程序，以评估电极形貌如何影响等离子体处理反应器中离子和自由基通量的均匀性，并提出补救或利用这些影响的方法。 在这项工作中，我们将建立和进一步发展现有的二维等离子体刻蚀和沉积反应器的混合模型。 等离子体特性的电极形貌的后果将评估蚀刻沟槽的轮廓，尘埃粒子陷阱，和差分晶片充电。

9404133 Kushner The Semiconductor Industry Association (SIA) has set the goal to achieve industry wide ).18um feature sizes in microelectronics devices by 2001 for wafer sizes as large as 40cm. These goals place extremely tight and tolerances on the uniformities of ion and radical fluxes to the surface are governed by the uniformity of their generation and the uniformity of potential gradients or flow fields which drive them to the substrate. These fluxes and gradients are highly sensitive to electrode topography which perturbs the plasma. Examples of electrode topography are the wafer itself, protruding clips from wafer holders bolt holes, and discontinuities in electrode materials on otherwise smooth surfaces. Plasma properties can even be influenced by metals or or dielectrics placed under the wafer. The researchers propose to perform a program of computer modeling to assess how electrode topography affects the uniformity of ion and radical fluxes to the substrate in plasma processing reactors, and propose methods to remediate or capitalize on those effects. In this effort we will build upon and further develop existing 2-dimensional hybird models of plasma etching and deposition reactors. The consequences of electrode topography on plasma properties will be assessed with regard to etching trench profiles, dust particle traps, and differential wafer charging.