Electrode Topography in Plasma Processing Reactors: Uniformity, Dust Particle Trapping and Differential Wafer Charging

9404133库什纳半导体行业协会（SIA）已经设定了实现全行业的目标。到2001年，微电子器件的18um特征尺寸可达到40cm的晶圆尺寸。这些目标对离子和自由基流到表面的均匀性提出了极其严格的要求，这些要求由它们产生的均匀性和驱动它们到达基材的势梯度或流场的均匀性决定。这些通量和梯度对扰乱等离子体的电极形貌高度敏感。电极形貌的例子是晶圆片本身，从晶圆支架螺栓孔中突出的夹子，以及在光滑表面上电极材料的不连续。等离子体的特性甚至会受到放置在晶圆下的金属或介质的影响。研究人员建议执行一个计算机建模程序，以评估电极形貌如何影响等离子体处理反应器中离子和自由基通量到基体的均匀性，并提出补救或利用这些影响的方法。在这项工作中，我们将建立并进一步发展现有的等离子体蚀刻和沉积反应器的二维混合模型。电极形貌对等离子体特性的影响将在蚀刻沟槽轮廓、粉尘颗粒陷阱和差动晶圆充电方面进行评估。

9404133 Kushner The Semiconductor Industry Association (SIA) has set the goal to achieve industry wide ).18um feature sizes in microelectronics devices by 2001 for wafer sizes as large as 40cm. These goals place extremely tight and tolerances on the uniformities of ion and radical fluxes to the surface are governed by the uniformity of their generation and the uniformity of potential gradients or flow fields which drive them to the substrate. These fluxes and gradients are highly sensitive to electrode topography which perturbs the plasma. Examples of electrode topography are the wafer itself, protruding clips from wafer holders bolt holes, and discontinuities in electrode materials on otherwise smooth surfaces. Plasma properties can even be influenced by metals or or dielectrics placed under the wafer. The researchers propose to perform a program of computer modeling to assess how electrode topography affects the uniformity of ion and radical fluxes to the substrate in plasma processing reactors, and propose methods to remediate or capitalize on those effects. In this effort we will build upon and further develop existing 2-dimensional hybird models of plasma etching and deposition reactors. The consequences of electrode topography on plasma properties will be assessed with regard to etching trench profiles, dust particle traps, and differential wafer charging.