ITR: Software-Hardware-Technology Co-Optimization for Ultra Low Power Architectures Via Delay Considerations

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Recently there has been considerable interest in the design of power/energy-aware electronics seeking to reduce the power consumption of military and consumer applications by over two orders of magnitude. This interest is driven by the power demands of today's high-speed, high-density, (portable) integrated electronics. Unless new power-efficient design methods are developed, there will be stringent limitations on the levels of electronics integration possible in the future as well as limitations on the speeds at which hardware can operate. Hardware portability will also be affected by battery size and weight. Simple calculations reveal that future microprocessors will dissipate several hundred watts of power unless drastic power reduction features are implemented. High power consumption and the associated high temperatures can also lead to reliability problems leading to early failure. If the trends in reduction of feature sizes and the increase in the levels of integration in silicon are to continue well into the future, the power consumption problem must be handled effectively and solved urgently.This research involves the study of hardware-software co-optimization methods to achieve ultra low power/energy consumption over a range of applications. Such co-optimization has been difficult in the past due to the complexity of the optimization problem and the fact that the optimization parameters stretch across software, hardware and technology parameters. While factors of energy savings up to 5X are possible using software, hardware and technology optimization individually, much larger savings are possible if a vertically integrated power optimization approach across software, hardware and technology boundaries is undertaken. To handle the complexity problem of such a vertically integrated power/energy minimization approach, a very simple optimization metric is proposed. This metric seeks to allocate delay to software and hardware modules in such a way that the delay of the module is proportional to the energy consumed by the module. Using such a metric, the problem of technology optimization (Vdd, Vt, device sizing) can be decoupled from that of system-level optimization without compromising the quality of the solution obtained. As long as the above metric is satisfied, software/hardware and technology optimizations can be done independently with high confidence that the resulting solution will be close to the optimum. Note that the proposed metric relies on the knowledge of the energy consumption of each module relative to other modules than on the absolute values of energy consumption of each module. The energy consumed by a hardware or software module relative to that of other modules is computed easily using simulation. It is conjectured that the use of the proposed power metric will simplify the complexity of the optimization problem to a degree that will allow much bigger, vertical optimizations to be performed across the software, hardware and technology boundaries.