CIF: Imperfection-Resilient Scalable Digital Signal Processing Algorithms and Architectures Using Significance Driven Computation

期望当今的集成电路在不断减小的功率预算下提供高质量/高性能水平。由于电源电压与功率成二次关系，电源电压调节是降低功耗的一种有效方法。然而，电源调整会增加所有计算路径中的延迟，并可能导致某些路径的计算不正确或不完整。除了功耗之外，工艺变化也是技术缩放的主要设计问题。电源电压可以按比例放大或逻辑门可以放大，以防止延迟故障，并实现更高的参数产量。然而，这样的技术是以增加功率和/或管芯面积为代价的。满足高成品率、低功耗和高质量的矛盾要求在纳米设计中变得非常具有挑战性。因此，需要一种可扩展的设计方法，其中在不断变化的功率约束和工艺条件下实现最小的输出质量劣化。此外，对于规定的功耗水平和工艺，设计方法必须考虑输入信号噪声和失真对数字信号处理（DSP）计算保真度的影响，并通过适当的算法和硬件设计确保在不同程度的噪声和失真下实现适度的输出质量降级。 该研究涉及开发一种系统方法，用于重组（转换）算法级计算、数据和底层硬件，以便在降低电源、增加工艺变化和降低输入信号质量的情况下实现DSP系统中最小的性能退化。已经观察到，对于DSP应用/系统，所有计算在成形输出响应方面并不同等重要。这些信息是利用调查人员开发合适的算法/架构，提供？是吧？输出质量与能耗（电源比例）与工艺变化引起的参数成品率与输入信号噪声之间的权衡。为了解决对过程变化的适应能力，调查人员根据输出敏感性确定这些系统的重要/不那么重要的组件。在这种情况下，随着电源电压和/或参数变化的缩放，如果在某些路径中存在潜在的延迟故障，则只有不太重要的计算受到影响。换句话说，使用精心设计的算法和架构，研究人员为重要/不那么重要的计算元件提供不等的错误保护（电压过缩放），从而实现了功耗的大幅改善，并使输出信号质量适度下降。

Present-day integrated circuits are expected to deliver high-quality/high-performance levels under ever-diminishing power budgets. Due to quadratic dependence of power on voltage, supply voltage scaling has been investigated as an effective method to reduce power. However, supply scaling increases the delays in all computation paths and can result in incorrect or incomplete computation of certain paths. Besides power dissipation, process variations also pose a major design concern with technology scaling. Supply voltage can be scaled-up or logic gates can be up-sized to prevent delay failures and to achieve higher parametric yield. However, such techniques come at the cost of increased power and/or die area. Meeting the contradictory requirements of high yield, low power and high quality are becoming exceedingly challenging in nanometer designs. Hence, there is a need for a scalable design methodology in which minimal output quality degradation is achieved under changing power constraints and process conditions. In addition, for a prescribed power consumption level and process, design methodology must take into account the effects of input signal noise and distortion on the fidelity of the Digital Signal Processing (DSP) computation and ensure that graceful output quality degradation is achieved under varying degrees of noise and distortion through proper algorithm and hardware design. The research involves development of a systematic methodology for reorganizing (transforming) algorithmic level computations, data and underlying hardware in such a way that minimum performance degradation in DSP systems is achieved under reduced power supply, increased process variations and reduced input signal quality. It has been observed that for DSP applications/systems, all computations are not equally important in shaping the output response. This information is exploited by the investigators to develop suitable algorithms/architectures that provide the ?right? trade-offs between output quality vs. energy consumption (supply scaling) vs. parametric yield due to process variations vs. input signal noise. To address resilience to process variations, the investigators identify the significant/not-so-significant components of such systems based on output sensitivities. Under such a scenario, with scaled supply voltage and/or parameter variations, if there are potential delay failures in some paths, only the less-significant computations are affected. In other words, using carefully designed algorithms and architectures, the investigators provide unequal error protection (under voltage over-scaling) to significant/not-so-significant computation elements, thereby achieving large improvements in power dissipation with graceful degradation in output signal quality.