CCF:SMALL:TIMING VARIATION RESILIENT SIGNAL PROCESSING: HARDWARE-ASSISTED CROSS-LAYER ADAPTATION

在这项研究中，提出了一种在算法、微架构和电路层面垂直集成的跨层时序变化弹性方法，并从后两个层面提供“硬件辅助”。这解决了现代深度扩展技术中工艺变化和随机延迟缺陷的影响以及电气错误的影响。 在层堆栈的最高层，该项目考虑算法级工作负载适应以及对底层硬件中由于低功耗/高速管道和算术单元操作而导致的间歇性错误的适应。这项研究的一个关键贡献是一种新的方法来准确确定流水线阶段的逻辑和算术单元何时完成计算。这使用了逻辑电路的波流水线操作的概念，并允许在几乎单个或几个门延迟内检测活动完成。这种完成感测允许流水线级比当前使用的同步时钟流水线更有效地“借用”或“借出”时间。此外，备份错误检测机制允许处理器管道可靠地运行，即使在完成感测电路中存在某种故障时也是如此。垂直集成控制算法用于在电路、微架构和算法（视频压缩）级别上调节功耗与性能与时序错误恢复能力，从而以最低的功耗在所需的视频吞吐量下提供所需的服务质量。通过这项研究工作，GaTech 在嵌入式 DSP 设计和测试以及极端工艺变化下的良率管理研究方面的课程开发将得到极大的促进。 PI 将开发一套关于实时数字信号处理系统中的电源管理和错误恢复能力的教材。 PI 将尽最大努力让少数民族暑期本科生研究体验 (SURE) 项目的本科生参与拟议的研究。通过有针对性的建议，也可以让高年级本科生项目学生参与这项研究。他们将参加H.O.T. Days@ Georgia Tech，一个为期一周的暑期项目，旨在向高中生介绍电气和计算机工程概念。主要参与将是与机器人的合作（LEGO Mindstorm，简单的功能）。佐治亚理工学院和奥本大学都积极鼓励本科生以及女性和少数族裔参与研究。奥本参与该项目还将提高 EPSCOR 州阿拉巴马州的研究能力。此外，来自位于奥本附近的历史黑人塔斯基吉大学的几名硕士生将在奥本大学攻读研究生课程。我们将鼓励这些学生中准备最充分的学生加入该项目并攻读博士学位。参与大学的课程。因此，该项目的资金将支持招募更多美国公民、女性和少数族裔参加研究生项目的目标。

In this research, a new vertically integrated cross-layer timing variation resilience methodology at the algorithm, microarchitecture and circuit levels, with "hardware-assistance" from the latter two levels is proposed. This addresses the effects of process variations and random delay defects in modern deeply scaled technologies as well as the effects of electrical bugs. At the highest level of the layer stack, the project considers algorithmic level workload adaptation as well as adaptation to intermittent errors in the underlying hardware due to low-power/high-speed pipeline and arithmetic unit operation. A key contribution of this research is a novel way to accurately determine when the logic and arithmetic units of pipeline stages have finished computation. This uses concepts from wave pipelined operation of logic circuits and allows activity completion detection within nearly a single or a few gate delays. Such completion sensing allows pipeline stages to "borrow" or "lend" time much more effectively than currently used synchronously clocked pipelines. In addition, backup error detection mechanisms allow the processor pipeline to operate reliably even when there is some kind of malfunction in the completion sensing circuitry. A vertically integrated control algorithm is used to modulate power vs. performance vs. timing error resilience at the circuit, microarchitecture and algorithm (video compression) levels to deliver the desired quality of service at the required video throughput with minimum power consumption. Through this research effort, the development of courses at GaTech in embedded DSP design and test, and yield management research under extreme process variations will be greatly facilitated. The PIs will develop a set of teaching materials on power management and error resilience in real-time digital signal processing systems. The PIs will make maximum effort to involve undergraduate students from the Summer Undergraduate Research Experience for minorities (SURE) program in the proposed research. It will also be possible to involve senior undergraduate project students in this research through targeted advisement. They will participate in H.O.T. Days@ Georgia Tech, a one-week long summer program designed to introduce high school students to electrical and computer engineering concepts. The key involvement will be in working with robots (LEGO Mindstorm, simple functions). Both Georgia Tech and Auburn University aggressively encourage participation of undergraduate students, as well as women and minorities in research. Auburn's participation in the project will also improve the research capabilities of Alabama, an EPSCOR state. Additionally, several master's students from the Historically Black Tuskegee University located near Auburn will take graduate courses at Auburn University. The best prepared among these students will be encouraged to join the project and Ph.D. programs at the participating universities. Thus, funding for this project will support the goals of recruiting more U.S. citizens, women and minorities to graduate programs.