Collaborative Resarch: Targeting Multi-Core Clock Performance Gains in the Face of Extreme Process Variations
Collaborative Resarch: Targeting Multi-Core Clock Performance Gains in the Face of Extreme Process Variations
批准号:
0903454
负责人:
Abhijit Chatterjee
金额:
$18.12万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-09-15 至 2013-08-31
中文摘要
这项研究的目标是克服限制多核处理器时钟频率的障碍,并通过技术扩展实现比目前可能的更快的时钟和数据吞吐速率。该方法是将硬件和软件基础设施设计成多核处理器,以实现单个处理器核的低成本比较测试和针对高速核操作的处理器电路的测试驱动调整。这项工作的智能优点在于,底层测试和适配算法能够从工艺核心中提取出它们在芯片间和芯片内工艺变化和电场退化情况下能够提供的最大性能。这种自适应是以有限的测试和诊断成本实现的,同时允许以不会导致系统崩溃的故障安全方式处理可能的“测试逃逸”。所生成的诊断信息用于调整各个处理器核心电路以提高速度。这项研究的更广泛影响包括在多核处理器上运行高级应用程序的能力,例如在未来的4G移动无线系统中运行高级应用程序的能力,包括高清晰度视频、交互式显示器、图像处理、数据挖掘算法和其他需要以低功耗实现高处理器吞吐量和高设备可靠性的普及计算任务。该项目还将通过原型演示、研讨会、讲习班、合作研究和学生在工业中的实习,在一个涉及电气工程、设备物理和计算机科学基本概念的新的跨学科领域对学生和工业人员进行培训。
英文摘要
The objective of this research is to overcome barriers limiting multicore processor clock frequencies and to achieve faster clock and data throughput rates with technology scaling than currently possible. The approach is to design hardware and software infrastructure into multicore processors that enables low cost comparison testing of the individual processor cores and test driven tuning of processor circuitry for high-speed core operation. The intellectual merit of this work lies in the ability of the underlying test and adaptation algorithms to extract the maximum amount of performance from the process cores that they are capable of delivering under inter and intra die process variations and electrical field degradation. Such adaptation is achieved with limited test and diagnosis cost while allowing possible "test escapes" to be handled in a fail-safe manner that does not result in a system crash. The diagnostics information generated is used to tune individual processor core circuitry for speed purposes. The broader impacts of this research include the ability to run advanced applications on multicore processors in, for example, future 4G mobile wireless systems including high definition video, interactive displays, image processing, data mining algorithms and other pervasive computing tasks that demand high processor throughput at low power for low heat dissipation and high device reliability. The project will also enable training of students and industry personnel in a new interdisciplinary field that involves fundamental concepts from electrical engineering, device physics and computer science through prototype demonstrations, seminars, workshops, cooperative research and student internships in industry.
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