SaTC: STARSS: Trojan Detection and Diagnosis in Mixed-Signal Systems Using On-The-Fly Learned, Precomputed and Side Channel Tests

在硅制造中使用外包使硬件容易受到称为特洛伊木马的恶意漏洞的影响，这些漏洞可能会导致集成电路(IC)在现场出现故障，类似于病毒在软件中表现出来的方式。虽然最近在木马检测和诊断方面取得了重大进展，但高分辨率特洛伊木马检测因硅制造工艺中增加的可变性而受到阻碍，使得木马可以隐藏在工艺可变性影响所必需的设计保护带后面。这项研究的主要目标是开发技术、算法和支持基础设施，以检测、诊断和缓解在现场部署后可能导致系统故障的各种电路中的木马影响，以及存在工艺变化影响的情况。混合信号和数字电路的底层木马检测技术使用测试激励优化算法，最大限度地提高应用于恶意硬件木马存在的测试的灵敏度。这样的算法得到了硬件的支持，用于向现场易受攻击的硬件设计提供测试。由于恶意插入芯片设计的漏洞的性质是事先未知的，调查人员使用即时学习算法来改进应用的测试，以暴露插入的特洛伊木马的影响。此外，还应用了预计算和旁路测试，使总体测试效率比现有方法提高了30倍。这些技术将大大提高美国工业和政府知识产权的安全性，并防止外部第三方篡改美国芯片设计。

The use of outsourcing in silicon manufacturing has rendered hardware susceptible to malicious bugs, called Trojans, that can cause an Integrated Circuit (IC) to fail in the field, similar to the way viruses manifest themselves in software. While there has been significant inroads into Trojan detection and diagnosis in the recent past, high-resolution Trojan detection has been hampered by the increased variability in silicon manufacturing processes, allowing Trojans to hide behind the design guardbands necessitated by process variability effects. The key objective of this research is to develop techniques, algorithms and support infrastructure for detecting, diagnosing and mitigating the effects of Trojans in a variety of circuits that can cause system malfunction after deployment in the field, in the presence of process variability effects.The underlying Trojan detection techniques for both mixed-signal and digital circuits use test stimulus optimization algorithms that maximize the sensitivities of the tests applied to the presence of malicious hardware Trojans. Such algorithms are supported by hardware for delivering the tests to vulnerable hardware designs in the field. Since the nature of bugs inserted maliciously into chip designs is not known apriori, the investigators use on-the-fly learning algorithms to refine the applied tests to expose the effects of inserted Trojans. In addition, precomputed and side-channel tests are applied to increase overall test effectiveness by up to 30X over existing methods. These techniques will enable significantly increased security of US industrial and government intellectual property and prevent tampering of US chip designs by external third parties.