NER: Exploring a Nanoscale Amorphous Silicon Thin Film Transistor

NER：探索纳米级非晶硅薄膜晶体管

• 批准号: 0301960
• 负责人: Yue Kuo
• 金额: $ 8万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-08-01 至 2004-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0301960&HistoricalAwards=false
• 关键词: NER; Exploring; Nanoscale; Amorphous; Silicon

The goal of this proposal is to explore a nanoscale amorphous silicon (a-Si:H) thin film transistor (TFT) prepared at a temperature of 250C or below. The success of this kind of device is critical to many future electronic, optoelectronic, biomedical devices, and circuits. We propose to investigate the feasibility of constructing such a functional TFT and to study its device characteristics.Currently, an a-Si:H TFT is mainly used for low-speed applications, such as in displays, imagers, and sensors, because of its low field-effect mobility. However, the cut off frequency of the transistor is inversely proportional to the square of the channel length. Therefore, the operation frequency of a nanoscale a-Si:H TFT, e.g., channel length less than 0.2 micrometer, can easily be higher than 1 MHz, which opens many new and advanced applications. We will investigate the feasibility of fabricating the nanoscale a-Si:H TFT. The TFT will have a self-aligned n + structure that is formed by the selective deposition or plasma doping method. The complete TFT will be characterized with respect to variations of the a-Si:H layer thickness and deposition processes. All experiments and electrical characterizations will be done in the principal investigators (PIs) Thin Film Microelectronics Research Laboratory, which is equipped with state-of-the-art instruments and facility.This is a multi-disciplinary research project. Graduate and undergraduate students of under-represented groups will be actively recruited to participate in the project. Students will obtain working knowledge and experience of nanoscale transistor fabrication, device characterization, and nano thickness thin film materials and analysis.

本计画的目的是探索在250 ℃或更低温度下制备的奈米级非晶硅薄膜电晶体。这种器件的成功对于许多未来的电子、光电、生物医学器件和电路至关重要。我们建议调查的可行性，构建这样一个功能的TFT和研究其器件characteristics.Currently，a-Si：H TFT主要用于低速应用，如在显示器，成像器，和传感器，因为它的低场效应迁移率。然而，晶体管的截止频率与沟道长度的平方成反比。因此，纳米级a-Si：H TFT的操作频率，例如，通道长度小于0.2微米，可以很容易地高于1 MHz，这开辟了许多新的和先进的应用。我们将探讨制作奈米级a-Si：H TFT的可行性。TFT将具有通过选择性沉积或等离子体掺杂方法形成的自对准n +结构。完整的TFT的特征在于相对于a-Si：H层厚度和沉积工艺的变化。所有的实验和电学特性将在主要研究者（PI）薄膜微电子研究实验室进行，该实验室配备了最先进的仪器和设备。这是一个多学科的研究项目。将积极招募代表性不足群体的研究生和本科生参加该项目。学生将获得纳米晶体管制造，器件表征和纳米厚度薄膜材料和分析的工作知识和经验。