NER: Exploring a Nanoscale Amorphous Silicon Thin Film Transistor

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The goal of this proposal is to explore a nanoscale amorphous silicon (a-Si:H) thin film transistor (TFT) prepared at a temperature of 250C or below. The success of this kind of device is critical to many future electronic, optoelectronic, biomedical devices, and circuits. We propose to investigate the feasibility of constructing such a functional TFT and to study its device characteristics.Currently, an a-Si:H TFT is mainly used for low-speed applications, such as in displays, imagers, and sensors, because of its low field-effect mobility. However, the cut off frequency of the transistor is inversely proportional to the square of the channel length. Therefore, the operation frequency of a nanoscale a-Si:H TFT, e.g., channel length less than 0.2 micrometer, can easily be higher than 1 MHz, which opens many new and advanced applications. We will investigate the feasibility of fabricating the nanoscale a-Si:H TFT. The TFT will have a self-aligned n + structure that is formed by the selective deposition or plasma doping method. The complete TFT will be characterized with respect to variations of the a-Si:H layer thickness and deposition processes. All experiments and electrical characterizations will be done in the principal investigators (PIs) Thin Film Microelectronics Research Laboratory, which is equipped with state-of-the-art instruments and facility.This is a multi-disciplinary research project. Graduate and undergraduate students of under-represented groups will be actively recruited to participate in the project. Students will obtain working knowledge and experience of nanoscale transistor fabrication, device characterization, and nano thickness thin film materials and analysis.