Collaborative Research: Defects Driven Reliability Modeling and Stress Burn-in Optimization in Nanoelectronics Manufacturing

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Yield and reliability are critical factors in determining the success of nanoelectronics manufacturing. They are traditionally evaluated separately based on different sources of information. Yield is generally estimated based on process control data such as measurements of manufacturing defects; while reliability prediction generally relies on lifetime data obtained from reliability tests. It is difficult to implement an end-of-line reliability assessment approach at early stages of a product's life cycle when data are limited. If successful, this award will enable a unified framework for managing yield, reliability, and stress burn-in in nanoelectronics manufacturing using process-control data. In addition, the integrated research and education plan associated with this award will provide interdisciplinary education and research opportunities for students from the underrepresented and impoverished Appalachian Ohio area and promote STEM education through K-12 outreach activities. This award focuses on yield and reliability of nanoelectronics products via spatiotemporal modeling of defects. The spatial modeling and temporal modeling of defects refer to modeling of the spatial distribution of defects and modeling of the growth of defects with time when devices are subject to stresses, respectively. A multidisciplinary team consisting of two PIs with expertise in nanoelectronics manufacturing and reliability engineering, respectively, is formed. Systematic accelerated destructive degradation tests followed by detailed physics-of-failure analysis will be conducted to explore failure mechanisms and to derive physics-based random defect-growth models. New yield models will be built based on the knowledge of defect size distribution and spatial distribution of defects. New reliability models will be suggested based on the defect-growth mechanisms and models. The reliability models will lead to new burn-in procedures. Ultra-narrow copper interconnect lines with sub 100 nanometers width prepared from a plasma-based etch process will be used as the testbed for the methodology.