Collaborative Research: Defects Driven Reliability Modeling and Stress Burn-in Optimization in Nanoelectronics Manufacturing

良率和可靠性是决定纳米电子制造成功与否的关键因素。传统上，它们是根据不同的信息来源分别评估的。产量通常是基于过程控制数据，如制造缺陷的测量来估计的；而可靠性预测通常依赖于从可靠性试验中获得的寿命数据。当数据有限时，很难在产品生命周期的早期阶段实施终线可靠性评估方法。如果获得成功，该合同将为利用过程控制数据管理纳米电子制造中的良率、可靠性和应力老化提供统一的框架。此外，与该奖项相关的综合研究和教育计划将为来自代表性不足和贫困的俄亥俄州阿巴拉契亚地区的学生提供跨学科教育和研究机会，并通过K-12外展活动促进STEM教育。该奖项的重点是通过缺陷的时空建模来提高纳米电子产品的产量和可靠性。缺陷的空间建模和时间建模分别是对器件受应力作用时缺陷的空间分布进行建模和对缺陷随时间的生长进行建模。成立了一个多学科团队，由两名分别在纳米电子制造和可靠性工程方面具有专业知识的pi组成。将进行系统的加速破坏性退化试验，然后进行详细的失效物理分析，以探索失效机制并推导基于物理的随机缺陷增长模型。基于缺陷尺寸分布和缺陷空间分布的知识，建立新的良率模型。基于缺陷生长机制和模型，提出了新的可靠性模型。可靠性模型将导致新的老化程序。采用等离子体蚀刻工艺制备的宽度小于100纳米的超窄铜互连线将作为该方法的测试平台。

Yield and reliability are critical factors in determining the success of nanoelectronics manufacturing. They are traditionally evaluated separately based on different sources of information. Yield is generally estimated based on process control data such as measurements of manufacturing defects; while reliability prediction generally relies on lifetime data obtained from reliability tests. It is difficult to implement an end-of-line reliability assessment approach at early stages of a product's life cycle when data are limited. If successful, this award will enable a unified framework for managing yield, reliability, and stress burn-in in nanoelectronics manufacturing using process-control data. In addition, the integrated research and education plan associated with this award will provide interdisciplinary education and research opportunities for students from the underrepresented and impoverished Appalachian Ohio area and promote STEM education through K-12 outreach activities. This award focuses on yield and reliability of nanoelectronics products via spatiotemporal modeling of defects. The spatial modeling and temporal modeling of defects refer to modeling of the spatial distribution of defects and modeling of the growth of defects with time when devices are subject to stresses, respectively. A multidisciplinary team consisting of two PIs with expertise in nanoelectronics manufacturing and reliability engineering, respectively, is formed. Systematic accelerated destructive degradation tests followed by detailed physics-of-failure analysis will be conducted to explore failure mechanisms and to derive physics-based random defect-growth models. New yield models will be built based on the knowledge of defect size distribution and spatial distribution of defects. New reliability models will be suggested based on the defect-growth mechanisms and models. The reliability models will lead to new burn-in procedures. Ultra-narrow copper interconnect lines with sub 100 nanometers width prepared from a plasma-based etch process will be used as the testbed for the methodology.