Architecture Design Methodologies for Embedded Communications Terminals

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Demand for broadband access anytime anywhere continues to grow. While it is important to reduce to power consumption in personal terminals, it is equally important to reduce silicon cost in applications such as settop boxes, DSL modems in central office or a wireless base stations. This proposal addresses low-power and/or low-cost implementations of a number of key building blocks which are common to many personal or central embedded communications terminals. Iterative decoders have found wide applications in wireless terminals, wireless infrastructure, satellite communications, etc. Recently, low-density parity check (LDPC) coders are receiving much attention due to their computation simplicity in every iteration, and ability to parallelize. These codes do not suffer from the error floor problem and are well suited for applications such as optical transmission and disk drives. Earlier work on parallel turbo decoder architectures will be extended to address efficient memory arbitration and memory management issues, and to reduce power consumption by appropriate parallelism level and memory selections. There is also interest in design of a new class of parallel turbo coders which can lend itself well for parallel implementations. In earlier work on LDPC coders, a new (3,k)-regular LDPC code which lends itself well for a partly-parallel implementations was demonstrated. The proposed effort will build upon this past work to generate more general LDPC coders. The desire to accommodate varying rates, varying frame sizes demands the generalization or construction otherwise of (j,k)-regular LDPC coders which can be implemented in partly-parallel manner. Placement and routing issues in these coders and memory size reduction issues will be addressed. The intellectual merit of this proposal lies in the unique ability to jointly consider algorithm and architectural issues to reduce power consumption of many components of broadband systems. Algorithm and architectural level power reduction can result in dramatic cost and power savings. The proposed effort will have an impact in various applications such as satellite communications, optical communications, storage devices, personal video recorders, settop boxes, wireless base stations and cell phones. The broader impacts will be far reaching. This research will pave the way for use of these technologies in industrial products. It will make an impact through research training of students working on this project, but the impact will be even greater through graduate education by transferring these research results to new or existing graduate classes.