SaTC: STARSS: Design of Secure and Anti-Counterfeit Integrated Circuits

硬件安全，无论是攻击还是防御，都不同于软件、网络和数据安全，因为攻击者可能会找到不留下痕迹的物理篡改设备的方法，并误导用户相信硬件是真实可信的。此外，新的攻击模式、非法回收和难以检测的木马的出现使硬件保护成为一项越来越具有挑战性的任务。安全硬件集成电路的设计需要新颖的身份验证方法，理想情况下基于多层保护。该项目开发了一个新的框架，用于在集成电路的设计中嵌入安全性和多层混淆的异构和层次。该项目将基于服务器的全局身份验证与来自第三方供应商的组件的本地身份验证相结合，减少了与服务器的通信，从而减少了通信开销以及身份验证中的错误。研究人员探索了通过有意的电压应力和认证层次中的权衡来增加基于SRAM的物理不可克隆功能（puf）的鲁棒性的新方法。该项目研究了基于有限状态机（FSM）状态转换图修改的混淆技术，以及使用从测试芯片收集的数据开发和验证的混淆度量。

Hardware security, whether for attack or defense, differs from software, network, and data security in that attackers may find ways to physically tamper with devices without leaving a trace, and mislead the user to believe that the hardware is authentic and trustworthy. Furthermore, the advent of new attack modes, illegal recycling, and hard-to-detect Trojans make hardware protection an increasingly challenging task. Design of secure hardware integrated circuits requires novel approaches for authentication that are ideally based on multiple layers of protection. This project develops a novel framework for embedding heterogeneity and hierarchy in security and obfuscation at multiple layers into the design of integrated circuits. The project uses a combination of server-based global authentication combined with local authentication of components from third-party vendors reduces communication with the server, thus reducing the communication overhead as well as error in authentication. The investigators explore new approaches to increasing robustness of SRAM based physical unclonable functions (PUFs) by intentional voltage stress, and the tradeoffs in hierarchies of authentication. The project investigates techniques for obfuscation based on modifications of finite state machine (FSM) state transition graphs, and obfuscation metrics that are developed and validated using data collected from test chips.