RIA: VLSI Architecture Designs for High-Speed Signal and Image Processing

该项目为数字信号和图像处理应用的高速实现开发算法和架构。基于先前关于高速线性递归和自适应数字滤波器的硬件高效实现的前瞻性，分解和增量计算技术的结果，开发了一种将这些算法转换为等效形式的方法，该方法可以在超出原始算法固有限制的采样率下运行。将这些技术扩展到非线性递归，如动态规划、量化器回路、自适应差分脉冲编码调制和自适应决策反馈均衡。目前正在研究这些算法在位串行、一点点串行和位并行架构中的实现。许多实时信号和图像处理算法的计算需求只能通过专门的实现来满足。专用设计的成功需要适当选择算法体系结构和实现方法。如本项目所研究的那样，对算法和体系结构方法的完整检查将为特定于应用程序的设计人员提供广泛的设计空间，可以利用它来获得更有效的实现。这项研究将影响专用信号和图像处理应用的VLSI实现的未来集成设计环境。

This project develops algorithms and architectures for high-speed implementations of digital signal and image processing applications. Based on previous results on lookahead, decomposition, and incremental computation techniques for hardware-efficient implementation of high- speed linear recursive and adaptive digital filters, a method is developed to transform these algorithms into equivalent forms, which can operate at sample rates beyond the inherent limits in the original algorithms. Extensions are being carried out on these techniques to nonlinear recursions, such as dynamic programming, quantizer loops, adaptive differential pulse code modulation, and adaptive decision feedback equalization. Implementations for these algorithms in bit- serial, nibble-serial, and bit-parallel architectures are currently under study. The computational needs in many real-time signal and image processing algorithms can only be met by dedicated implementations. Success of dedicated designs require appropriate choice of algorithms architectures, and implementation methodologies. A complete examination of the algorithm and architecture approaches, as studied in this project, will provide the application-specific designer a wide design space, which can be exploited to obtain more efficient implementations. This research will impact future integrated design environments for VLSI implementations of dedicated signal and image processing applications.