ITR: Built-in Test for High Speed/RF Mixed-Signal Electronics

项目名称：ITR：高速/RF混合信号电子器件的内置测试提案编号：0325555机构：格鲁吉亚技术学院，GAPRINCIPAL认证人：Abhijit Chatterjee（主要研究者）提案编号：0325371机构：美国德克萨斯州，奥斯汀，德克萨斯州主要经销商：Jacob Abrahams（coPI）提案编号：0325426机构：奥本大学，阿拉巴马州Singh（coPI）提案编号：0325340机构：佛罗里达大学校长：William R. 艾森施塔特（coPI）摘要：近年来，有线通信/无线/高速IC制造领域出现了巨大的增长。虽然设计界已经将设计范围推向了未来，但测试障碍还没有跟上高速集成无线和有线通信设计的测试要求。每一个生产出来的IC在发货给客户之前都需要根据其设计规格进行测试。随着这些IC的速度提高，在制造生产中测试这些IC所需的测试仪的要求也在提高。2 GHz以上的高速测试仪非常昂贵。因此，对于超过几GHz（2 - 25 GHz）的速度，高速/RF系统的内置测试（BIT）是一个非常有吸引力的解决方案。内建测试是指在集成电路中加入测试电路，以方便制造测试过程。通过这种方式，许多测试功能都是在“片上”执行的，从而减少了对高速（昂贵）外部测试仪的需求。在不久的将来，测试成本预计将上升到复杂通信集成电路总制造成本的40%左右，因此，使用内置测试预计将显著影响集成电路本身的制造成本和公司在市场上的竞争能力。内置测试方法背后的核心概念很容易理解。本文提出了一种新的高速/射频电路BIT测试方法，该方法不直接测量被测IC的高速测试指标，而是采用交替测试的方法。替代测试是紧凑型测试，比原始规格测试更容易运行，但包含与原始测试本身一样多（或更多）的被测电路性能信息。此外，可以设计这些测试，以便基于使用模拟电路对模拟信号的分析来做出通过-失败决定。通过这种方式，解决了两个问题：（a）能够使用简单的片上测试资源和低成本的外部测试器来测量复杂的高速测试规范，以及（B）能够分析非常高速的信号（2 Ghz）而不需要对它们进行解调（在这些频率下，这种数字化器不可用或者非常昂贵）。拟议的工作是跨学科的，将涉及使用计算机算法，模拟/RF电路设计，数学和统计学以及基础电气工程和设备物理学的概念。

PROJECT TITLE: ITR: Built-In Test of High Speed/RF Mixed Signal ElectronicsPROPOSAL NO.: 0325555INSTITUTION: Georgia Inst. Technology, GAPRINCIPAL INVESTIGATOR: Abhijit Chatterjee (lead PI)PROPOSAL NO.: 0325371INSTITUTION: U. Texas, Austin, TXPRINCIPAL INVESTIGATOR: Jacob Abrahams (coPI)PROPOSAL NO.: 0325426INSTITUTION: Auburn University, AlabamaPRINCIPAL INVESTIGATOR: Adit D. Singh (coPI)PROPOSAL NO.: 0325340INSTITUTION: University of FloridaPRINCIPAL INVESTIGATOR:William R. Eisenstadt (coPI)ABSTRACT:In the recent past, there has been a tremendous surge in the wired communications/wireless/high-speed IC manufacturing sector. While the design community has pushed the design envelope far into the future, the test barriers have not kept pace with the test requirements of high speed, integrated wireless and wired communications designs. Every IC that is manufactured, needs to be tested against its design specifications before shipment to the customer. As the speeds of these ICs increase, so do the requirements of the testers needed to test these ICs in manufacturing production. High-speed testers above 2 GHz are prohibitively expensive. Consequently, for speeds beyond a few GHz (2 - 25 GHz), built-in test (BIT) of high-speed/RF systems is a very attractive solution. Built-in test involves incorporation of test circuitry in the IC itself to facilitate the manufacturing test process. In this way, many of the test functions are performed "on-chip," alleviating the need for a high-speed (expensive) external tester. Since test cost is projected to escalate to about 40% of the total manufacturing cost of complex communications ICs in the near future, the use of built-in test is expected to significantly impact the cost of the manufactured ICs themselves and the ability of companies to compete in the marketplace.The core concept behind the proposed built-in test methodology is easy to follow. Instead of directly measuring the high-speed test specifications of the IC-under-test, a new paradigm for BIT of high-speed/RF circuits using alternate tests is proposed. Alternate tests are compact tests that are much more simpler to run than the original specification tests but contain as much information (or more) about the performance of the circuit-under-test as the original tests themselves. Furthermore, it is possible to design these tests so that pass-fail decisions can be made, based on analysis of analog signals using analog circuitry. In this way, two problems are solved: (a) that of being able to measure complex high-speed test specifications using simple on-chip test resources and a low-cost external tester, and (b) that of being able to analyze very high-speed signals ( 2 Ghz) without the need to digitize them (such digitizers are not available or are very expensive at these frequencies). The proposed work is interdisciplinary and will involve the use of concepts from computer algorithms, analog/RF circuit design, mathematics and statistics and fundamental electrical engineering and device physics.