SGER: Novel Phonon Engineering Concepts for Nanoscale Devices and 3D Integrated Circuits

SGER：纳米级器件和 3D 集成电路的新颖声子工程概念

• 批准号: 0407848
• 负责人: Alexander Balandin
• 金额: $ 5.98万
• 依托单位: University of California-Riverside
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-07-01 至 2005-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0407848&HistoricalAwards=false
• 关键词: SGER; Novel; Phonon; Engineering; Concepts

The problem of heat removal becomes crucial for continuing CMOS downscaling, beyond CMOS nanoscale concepts, ULSI, and 3D architecture proposals. Conventional heat removal methods and post device-design / packaging level cooling solutions fail to work at nanoscale and in 3D architectures. This proposal introduces a drastic philosophy change in heat removal, e.g. thermal management features incorporated at the materials / device level, as well as two new radical concepts of heat removal via phonon engineering such as (i) thermal conductivity enhancement of the material along chosen directions via proper engineering of device heterostructures and (ii) smart arrangement of the nanoscale devices in ULSI circuits or in 3D architectures to achieve acoustic phonon interference and phonon annihilation, e.g. local cooling, in pre-determined locations.

除了CMOS纳米级概念、ULSI和3D架构提案之外，散热问题对CMOS的持续降阶至关重要。传统的散热方法和后器件设计/封装级冷却解决方案无法在纳米级和3D架构中工作。该提案在散热方面引入了一个巨大的理念变化，例如在材料/设备层面纳入热管理功能，以及通过声子工程来消除热量的两个新的激进概念，例如(i)通过适当的器件异质结构工程来增强材料沿着选定方向的导热性；（ii）在ULSI电路或3D架构中对纳米级器件进行智能安排，以实现声子干涉和声子湮灭，例如在预定位置的局部冷却。