Interconnect Planning in Placement and Logic Synthesis

布局和逻辑综合中的互连规划

• 批准号: 0427821
• 负责人: Malgorzata Marek-Sadowska
• 金额: $ 30万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-09-15 至 2008-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0427821&HistoricalAwards=false
• 关键词: Interconnect; Planning; Placement; Logic; Synthesis

PROPOSAL NO: 0427821INSTITUTION: University of California-Santa BarbaraPRINCIPAL INVESTIGATOR: Marek-Sadowska, MalgorzataTITLE: Interconnect Planning in Placement and Logic SynthesisAbstract:Due to the tremendous progress in technology, VLSI chips become very large and complex, and this trend is expected to continue. The increased chip complexity causes that average interconnect lengths increase and proportionally larger and larger fraction of chip's area is occupied by interconnects. This tendency is not only caused by the increased design complexities, but also by the fact that the existing CAD tools do not scale well. This proposal addresses several issues related to interconnects in submicron technologies at design abstractions higher than routing. In design flow, placement is a step which to a large extent, determines the interconnect characteristics. The intension is to integrate into placement several objectives, which are conventionally solved by point tools on placed (and often on routed) designs. The goal is to develop an efficient, multi-objective incremental placer capable of offering well-understood tradeoffs. Besides incremental corrections at the placement level, methodologies of circuit optimization integrated into placement flow will be studied and developed. Timing-driven placement flow will integrate retiming, sequential budgeting, skew optimization, and simultaneous global routing. It is expected that the work at the placement level will result in efficient optimization techniques and will help in formulating requirements for the higher level toolsto create easier routable designs.

提案编号：0427821机构：加州大学圣巴巴拉分校校长：Marek-Sadowska，Malgorzata标题：布局和逻辑合成中的互连规划摘要：由于技术的巨大进步，超大规模集成电路芯片变得非常大和复杂，预计这一趋势将继续下去。芯片复杂性的增加导致平均互连长度增加，并且互连占用的芯片面积比例越来越大。这种趋势不仅是由于设计复杂性的增加，而且由于现有的CAD工具不能很好地扩展。这个建议解决了几个问题，在亚微米技术的互连在设计抽象高于路由。在设计流程中，布局是很大程度上决定互连特性的一个步骤。其意图是将几个目标集成到布局中，这些目标通常通过放置（通常是布线）设计上的点工具来解决。我们的目标是开发一个有效的，多目标的增量砂矿能够提供良好的理解权衡。除了在布局水平的增量校正，电路优化集成到布局流程的方法将被研究和开发。时序驱动的布局流程将集成重时序，顺序预算，偏斜优化，同时全球布线。预计在布局水平的工作将导致有效的优化技术，并将有助于制定更高层次的工具，以创建更容易的布线设计的要求。