Interconnect Planning in Placement and Logic Synthesis

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PROPOSAL NO: 0427821INSTITUTION: University of California-Santa BarbaraPRINCIPAL INVESTIGATOR: Marek-Sadowska, MalgorzataTITLE: Interconnect Planning in Placement and Logic SynthesisAbstract:Due to the tremendous progress in technology, VLSI chips become very large and complex, and this trend is expected to continue. The increased chip complexity causes that average interconnect lengths increase and proportionally larger and larger fraction of chip's area is occupied by interconnects. This tendency is not only caused by the increased design complexities, but also by the fact that the existing CAD tools do not scale well. This proposal addresses several issues related to interconnects in submicron technologies at design abstractions higher than routing. In design flow, placement is a step which to a large extent, determines the interconnect characteristics. The intension is to integrate into placement several objectives, which are conventionally solved by point tools on placed (and often on routed) designs. The goal is to develop an efficient, multi-objective incremental placer capable of offering well-understood tradeoffs. Besides incremental corrections at the placement level, methodologies of circuit optimization integrated into placement flow will be studied and developed. Timing-driven placement flow will integrate retiming, sequential budgeting, skew optimization, and simultaneous global routing. It is expected that the work at the placement level will result in efficient optimization techniques and will help in formulating requirements for the higher level toolsto create easier routable designs.