A Multi-level/multi-faceted Framework for Energy-efficient Application-Specific Instruction Set Processor Synthesis

节能型专用指令集处理器综合的多层次/多方面框架

• 批准号: 0541102
• 负责人: Yunsi Fei
• 金额: $ 27.5万
• 依托单位: University of Connecticut
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-04-01 至 2011-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541102&HistoricalAwards=false
• 关键词: Multi; level; multi; faceted; Framework

Application-specific instruction set processors (ASIPs) promise to offer a good tradeoff between flexibility and performance, and have been adopted widely. However, most of the research work has focused on improving performance specifically, taking a flawed assumption that low execution time always leads to energy savings. Energy-optimized ASIP synthesis and associated problems have escaped thorough scrutiny. The objective of the proposed work is to develop a new framework for energy-efficient ASIP synthesis, where a fast and accurate energy evaluation tool will be exploited to aid design space exploration, various energy optimization techniques at different levels will be applied throughout the design flow, and multiple facets of system design will be re-examined from the energy perspective. First, a hybrid energy estimation model for configurable and extensible processors in the early design cycle will be designed. The energy macro-model will capture not only the extensibility provided by additional custom hardware components through a structural macro-model, but also the configurability of the baseline processor through an instruction-level macro-model, including register file size, and pipeline issue width, etc. A set of energy-optimization techniques will be utilized during ASIP design flow systematically. Focus will be on multi-level application-specific optimization techniques, ranging from data-level storage size adaptation, to task-level parallelism extraction, up to system-level spurious switching activity suppression. Multiple facets of the system design to achieve best energy efficiency will be investigated. The proposed work will be a general study of several core technologies to enable the design, spanning the fields of compilation techniques, design space exploration, customized processor architecture generation, and high-level synthesis methodologies and tools. The ultimate goal is to expand the paradigm of ASIP synthesis along an important but not well-investigated dimension of energy efficiency. The framework and tools developed will provide an ideal mechanism through which students can interact with tangible examples of computer architecture, design hierarchy, hardware-software co-design, compiler concepts - it will allow them to rapidly prototype systems, experiment with new ideas, and thereby build intuition about embedded processor and application design.

专用指令集处理器（ASIP）承诺提供灵活性和性能之间的良好平衡，并已被广泛采用。然而，大多数研究工作都专门关注提高性能，并采取了一个有缺陷的假设，即低执行时间总是会节省能源。能量优化的ASIP合成和相关问题已经逃脱了彻底的审查。拟议的工作的目标是开发一个新的框架，能源效率的ASIP合成，其中一个快速和准确的能源评估工具将被利用，以帮助设计空间探索，在不同层次的各种能源优化技术将应用于整个设计流程，并从能源的角度重新审视系统设计的多个方面。首先，在早期的设计周期中的可配置和可扩展的处理器的混合能量估计模型将被设计。能量宏模型不仅通过结构化宏模型捕获额外的定制硬件组件提供的可扩展性，而且通过配置级宏模型捕获基线处理器的可配置性，包括寄存器文件大小和流水线发布宽度等。在ASIP设计流程中，将系统地利用一组能量优化技术。重点将放在多层次的应用程序特定的优化技术，从数据级存储大小的适应，任务级并行提取，到系统级的虚假切换活动抑制。将研究系统设计的多个方面，以实现最佳的能源效率。拟议的工作将是几个核心技术的一般性研究，使设计，跨越领域的编译技术，设计空间探索，定制的处理器架构生成，高层次的综合方法和工具。最终的目标是扩展ASIP合成的范例沿着一个重要的，但没有充分调查的能源效率的维度。开发的框架和工具将提供一种理想的机制，通过这种机制，学生可以与计算机体系结构，设计层次，硬件-软件协同设计，编译器概念的有形示例进行交互-这将使他们能够快速原型系统，实验新的想法，从而建立对嵌入式处理器和应用程序设计的直觉。