A Multi-level/multi-faceted Framework for Energy-efficient Application-Specific Instruction Set Processor Synthesis

特定于应用程序的指令集处理器（Application-specific instruction set processor, asip）有望在灵活性和性能之间取得良好的平衡，并已被广泛采用。然而，大多数的研究工作都集中在提高性能上，并有一个错误的假设，即低执行时间总能节省能源。能源优化的ASIP合成及其相关问题没有得到彻底的审查。提出的工作目标是开发一个新的节能ASIP综合框架，其中将利用快速准确的能源评估工具来帮助设计空间探索，在整个设计流程中应用不同层次的各种能源优化技术，并从能源角度重新审视系统设计的多个方面。首先，设计了可配置和可扩展处理器在早期设计周期的混合能量估计模型。能量宏模型不仅通过结构宏模型捕获额外定制硬件组件提供的可扩展性，还通过指令级宏模型捕获基线处理器的可配置性，包括寄存器文件大小和管道问题宽度等。在ASIP设计流程中，将系统地应用一套能量优化技术。重点将放在多层次特定于应用程序的优化技术上，从数据级存储大小适应，到任务级并行性提取，再到系统级杂散切换活动抑制。系统设计的多个方面，以达到最佳的能源效率将被调查。提议的工作将是对几项核心技术的一般性研究，以实现设计，涵盖编译技术、设计空间探索、定制处理器架构生成以及高级综合方法和工具等领域。最终目标是沿着一个重要但尚未得到充分研究的能源效率维度扩展ASIP综合范例。所开发的框架和工具将提供一种理想的机制，通过这种机制，学生可以与计算机体系结构、设计层次、硬件软件协同设计、编译器概念等有形的例子进行交互——这将使他们能够快速构建系统原型，试验新的想法，从而建立对嵌入式处理器和应用程序设计的直觉。

Application-specific instruction set processors (ASIPs) promise to offer a good tradeoff between flexibility and performance, and have been adopted widely. However, most of the research work has focused on improving performance specifically, taking a flawed assumption that low execution time always leads to energy savings. Energy-optimized ASIP synthesis and associated problems have escaped thorough scrutiny. The objective of the proposed work is to develop a new framework for energy-efficient ASIP synthesis, where a fast and accurate energy evaluation tool will be exploited to aid design space exploration, various energy optimization techniques at different levels will be applied throughout the design flow, and multiple facets of system design will be re-examined from the energy perspective. First, a hybrid energy estimation model for configurable and extensible processors in the early design cycle will be designed. The energy macro-model will capture not only the extensibility provided by additional custom hardware components through a structural macro-model, but also the configurability of the baseline processor through an instruction-level macro-model, including register file size, and pipeline issue width, etc. A set of energy-optimization techniques will be utilized during ASIP design flow systematically. Focus will be on multi-level application-specific optimization techniques, ranging from data-level storage size adaptation, to task-level parallelism extraction, up to system-level spurious switching activity suppression. Multiple facets of the system design to achieve best energy efficiency will be investigated. The proposed work will be a general study of several core technologies to enable the design, spanning the fields of compilation techniques, design space exploration, customized processor architecture generation, and high-level synthesis methodologies and tools. The ultimate goal is to expand the paradigm of ASIP synthesis along an important but not well-investigated dimension of energy efficiency. The framework and tools developed will provide an ideal mechanism through which students can interact with tangible examples of computer architecture, design hierarchy, hardware-software co-design, compiler concepts - it will allow them to rapidly prototype systems, experiment with new ideas, and thereby build intuition about embedded processor and application design.