A Multi-level/multi-faceted Framework for Energy-efficient Application-Specific Instruction Set Processor Synthesis

专用指令集处理器(ASIP)承诺在灵活性和性能之间提供良好的折衷，并已被广泛采用。然而，大多数研究工作都集中在具体的性能改进上，采用了一个有缺陷的假设，即执行时间较短总是会导致能源节约。能源优化的ASIP合成和相关问题没有得到彻底的审查。拟议工作的目标是开发一个新的节能ASIP综合框架，其中将利用快速和准确的能源评估工具来辅助设计空间探索，在整个设计流程中将应用不同级别的各种能源优化技术，并将从能源角度重新审查系统设计的多个方面。首先，在可配置和可扩展处理器的早期设计周期中设计了一个混合能量估计模型。能量宏模型不仅通过结构宏模型捕捉额外定制硬件组件提供的可扩展性，而且通过指令级宏模型捕捉基线处理器的可配置性，包括寄存器堆大小和流水线发布宽度等。在ASIP设计流程中将系统地使用一套能量优化技术。重点将放在多级别特定于应用的优化技术上，范围从数据级存储大小调整到任务级并行性提取，再到系统级杂散开关活动抑制。将对系统设计的多个方面进行调查，以实现最佳的能源效率。拟议的工作将是对实现设计的几项核心技术的一般性研究，涉及编译技术、设计空间探索、定制处理器体系结构生成以及高级综合方法和工具等领域。最终目标是沿着能源效率的一个重要但尚未得到充分研究的维度扩展ASIP合成的范例。开发的框架和工具将提供一种理想的机制，通过该机制，学生可以与计算机体系结构、设计层次、软硬件协同设计、编译器概念的有形示例进行交互-它将使他们能够快速制作系统原型，试验新想法，从而建立对嵌入式处理器和应用程序设计的直觉。

Application-specific instruction set processors (ASIPs) promise to offer a good tradeoff between flexibility and performance, and have been adopted widely. However, most of the research work has focused on improving performance specifically, taking a flawed assumption that low execution time always leads to energy savings. Energy-optimized ASIP synthesis and associated problems have escaped thorough scrutiny. The objective of the proposed work is to develop a new framework for energy-efficient ASIP synthesis, where a fast and accurate energy evaluation tool will be exploited to aid design space exploration, various energy optimization techniques at different levels will be applied throughout the design flow, and multiple facets of system design will be re-examined from the energy perspective. First, a hybrid energy estimation model for configurable and extensible processors in the early design cycle will be designed. The energy macro-model will capture not only the extensibility provided by additional custom hardware components through a structural macro-model, but also the configurability of the baseline processor through an instruction-level macro-model, including register file size, and pipeline issue width, etc. A set of energy-optimization techniques will be utilized during ASIP design flow systematically. Focus will be on multi-level application-specific optimization techniques, ranging from data-level storage size adaptation, to task-level parallelism extraction, up to system-level spurious switching activity suppression. Multiple facets of the system design to achieve best energy efficiency will be investigated. The proposed work will be a general study of several core technologies to enable the design, spanning the fields of compilation techniques, design space exploration, customized processor architecture generation, and high-level synthesis methodologies and tools. The ultimate goal is to expand the paradigm of ASIP synthesis along an important but not well-investigated dimension of energy efficiency. The framework and tools developed will provide an ideal mechanism through which students can interact with tangible examples of computer architecture, design hierarchy, hardware-software co-design, compiler concepts - it will allow them to rapidly prototype systems, experiment with new ideas, and thereby build intuition about embedded processor and application design.