A Multi-level/multi-faceted Framework for Energy-efficient Application-Specific Instruction Set Processor Synthesis

节能型专用指令集处理器综合的多层次/多方面框架

• 批准号: 0541102
• 负责人: Yunsi Fei
• 金额: $ 27.5万
• 依托单位: University of Connecticut
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-04-01 至 2011-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541102&HistoricalAwards=false
• 关键词: Multi; level; multi; faceted; Framework

Application-specific instruction set processors (ASIPs) promise to offer a good tradeoff between flexibility and performance, and have been adopted widely. However, most of the research work has focused on improving performance specifically, taking a flawed assumption that low execution time always leads to energy savings. Energy-optimized ASIP synthesis and associated problems have escaped thorough scrutiny. The objective of the proposed work is to develop a new framework for energy-efficient ASIP synthesis, where a fast and accurate energy evaluation tool will be exploited to aid design space exploration, various energy optimization techniques at different levels will be applied throughout the design flow, and multiple facets of system design will be re-examined from the energy perspective. First, a hybrid energy estimation model for configurable and extensible processors in the early design cycle will be designed. The energy macro-model will capture not only the extensibility provided by additional custom hardware components through a structural macro-model, but also the configurability of the baseline processor through an instruction-level macro-model, including register file size, and pipeline issue width, etc. A set of energy-optimization techniques will be utilized during ASIP design flow systematically. Focus will be on multi-level application-specific optimization techniques, ranging from data-level storage size adaptation, to task-level parallelism extraction, up to system-level spurious switching activity suppression. Multiple facets of the system design to achieve best energy efficiency will be investigated. The proposed work will be a general study of several core technologies to enable the design, spanning the fields of compilation techniques, design space exploration, customized processor architecture generation, and high-level synthesis methodologies and tools. The ultimate goal is to expand the paradigm of ASIP synthesis along an important but not well-investigated dimension of energy efficiency. The framework and tools developed will provide an ideal mechanism through which students can interact with tangible examples of computer architecture, design hierarchy, hardware-software co-design, compiler concepts - it will allow them to rapidly prototype systems, experiment with new ideas, and thereby build intuition about embedded processor and application design.

特定于应用程序的指令设置处理器（ASIP）承诺在灵活性和性能之间提供良好的权衡，并已被广泛采用。但是，大多数研究工作都集中在具体提高绩效上，这是一个有缺陷的假设，即低执行时间总是可以节省能源。能量优化的ASIP合成和相关问题已彻底审查。拟议工作的目的是为节能ASIP合成开发一个新的框架，其中将利用快速准确的能源评估工具来帮助设计空间探索，在整个设计流中，将应用不同级别的各种能量优化技术，并且从能量角度来看，系统设计的多个方面将重新检查。首先，将设计针对早期设计周期中可配置和可扩展处理器的混合能量估计模型。能量宏模型不仅将通过结构上的宏模型捕获其他自定义硬件组件提供的可扩展性，还将通过指令级别的宏观模型（包括寄存器文件尺寸和管道发行宽度等）来捕获基线处理器的配置性。一组能量允许的技术将在ASIP设计过程中使用。重点将集中在多级应用程序特定的优化技术上，从数据级存储大小适应到任务级并行性提取，再到系统级的伪造开关活动活动抑制。将研究系统设计的多个方面，以实现最佳能源效率。拟议的工作将是对几种核心技术的一般研究，以实现设计，涵盖编译技术，设计空间探索，定制的处理器架构生成以及高级合成方法和工具的领域。最终目标是将ASIP合成的范式扩展到重要但没有良好的能源效率维度。开发的框架和工具将提供一种理想的机制，通过该机制，学生可以通过该机制与计算机架构，设计层次结构，硬件 - 软件共同设计，编译器概念的切实示例进行交互 - 它将允许他们快速原型系统，尝试新思想，从而构建有关嵌入式处理器和应用程序设计的直觉。