Switching Techniques and Architectures for Performance-Adaptive, Power-Aware Hybrid Opto-Electronic Interconnects

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Switching Techniques and Architectures for Performance-Adaptive, Power-Aware Hybrid Opto-Electronic InterconnectsAhmed Louri, University of Arizona0725765Intellectual Merits: To address the performance and power requirements of future interconnects for High Performance Computing (HPC) systems, this research proposes to exploit the recent significant advances in optical device technology to develop new bandwidth-reconfigurable and power-efficient photonic switching techniques, reliable interconnect architectures, and efficient reconfiguration control management strategies. These switching techniques, interconnect architectures, and management strategies will be seamlessly integrated with current HPC systems. This will enable HPC architectures to dynamically adapt to communication traffic patterns and re-allocate bandwidth at run-time. Power consumption will also be monitored and dynamically managed to optimize its use. Reliability and scalability will be addressed through the selection of appropriate optical devices, effective use of dynamic bandwidth and power management techniques, and innovative interconnect topologies. On the technology side, this research explores both active and passive optical technology design space. For passive technology, we propose to extend the switching capabilities of arrayed waveguide gratings (AWGs) to implement dynamic reconfiguration. For active technology, we propose the use of silicon based optical ring resonators, which have a small footprint, reduced power consumption, and high bandwidth characteristics, appropriate for HPC systems. Broader Impact: The success of this research is likely to have a significant impact on the design of next generation HPC and communication systems. The proposed research will provide novel solutions to fundamental communication problems facing future HPC systems and will make significant advances in understanding the interplay between the performance and power consumption. Additionally, it will offer valuable insight and solutions to critical design problems in the use of integrated hybrid systems for high-speed computation and communications. It is also likely to spawn new areas of research such as power-aware opto-electronic systems, fault-tolerant opto-electronic networks and systems, and high-speed on-chip optical interconnects. The proposed research will also provide multi-disciplinary training to undergraduate and graduate students by combining device technology, computer architecture, modeling and simulation, and physical demonstration.