SHF: Small: Collaborative Research: Power-Efficient and Reliable 3D Stacked Reconfigurable Photonic Network-on-Chips for Scalable Multicore Architectures

随着数字电路的大规模集成，单芯片上的功耗以惊人的速度增长，多核设计已成为提高性能的唯一技术。市场上已经有数十到数百个核的多核可用，未来的预测要求芯片上有数千个核。为了通过多核实现可扩展的计算性能，核之间的通信还应扩展带宽，同时显著降低功耗。扩展片上通信结构(称为片上网络(NOC))的性能已被证明是传统金属互连的一个重大挑战，原因是基本的信令问题，如功耗、电磁干扰、串扰和反射。一些研究和路线图表明，像光子学这样的颠覆性技术解决方案有可能缓解未来多核的关键带宽、功率和延迟挑战。这项研究旨在利用光子互连和3D堆叠技术的独特优势，为未来的多核开发可扩展、节能、带宽可重构和可靠的片上网络。提出的研究有三个目标：第一，研究和开发3D叠层光子NoC架构和拓扑，以最大化性能和提高能量效率。其次，它将开发运行时重新配置技术，使网络适应应用程序的通信需求，从而提高每个应用程序的性能。第三，这将产生一个广泛的建模和仿真框架，用于设计和验证未来的光子NoC体系结构。这项研究具有独特的优势，可以利用两种新兴技术，即光子学和3D堆叠来应对多核挑战，并将显著造福社会。这项拟议的研究对于我们社会所依赖的计算性能的持续增长至关重要，并将导致从智能手机到笔记本电脑的各种数字设备具有更快的响应时间和更高的可靠性。通过研究高能效和高带宽的光子-3D NoC体系结构的设计，该提案描述了一种将技术、算法和应用相结合的变革性和可行性方法。支持构建可扩展多核的研究。这项研究的交叉性质将在几个领域培育新的研究方向，包括技术/能源感知NoC设计、新颖的计算机体系结构以及新兴技术的尖端建模和仿真工具。这项研究还将通过将发现与教学和培训相结合，在教育中发挥重要作用。几名研究生将直接参与项目的所有阶段，他们的论文和论文的核心部分将从这些阶段派生出来。它还将使更多的研究生和本科生受益，因为它将新的研究纳入由私人投资促进机构教授的几门关于计算机体系结构和并行处理的课程。最后，拟议研究的结果和结论将通过技术出版物和演示文稿传播给研究人员、工程师和教育工作者。

As power dissipation on a single-chip is increasing at an alarming rate due to massive integration of digital circuits, multicore design has become the only technique to scale performance. Multicores with tens to hundreds of cores are already available in the marketplace and future projections call for thousands of cores on the chip. To achieve scalable computing performance from the multicores, the communication between cores should also scale in bandwidth while significantly reducing the power consumption. Scaling the performance of the on-chip communication fabric, called the Network-on-Chip (NoC), has proven to be a significant challenge with traditional metallic interconnects due to fundamental signaling issues such as power dissipation, electromagnetic interference, crosstalk and reflections. Several studies and roadmaps have indicated that disruptive technology solutions such as photonics have the potential to alleviate the critical bandwidth, power and latency challenges of future multicores. This research seeks to exploit the unique advantages of photonic interconnects and 3D stacking technologies to develop scalable, energy-efficient, bandwidth-reconfigurable and reliable NoCs for future multicores. There are three goals of the proposed research; first, it will investigate and develop 3D stacked photonic NoC architectures and topologies that maximize performance and improve energy-efficiency. Second, it will develop runtime reconfiguration techniques that can adapt the network to the communication needs of the application, thereby improving performance on a per-application basis. Third, it will result in an extensive modeling and simulation framework to be used for designing and validating future photonic NoC architectures.This research has far reaching broader impacts. This research is uniquely positioned to leverage two emerging technologies namely photonics and 3D stacking to meet the multicore challenge and will significantly benefit society. The proposed research is essential to continue the growth of computing performance that our society depends upon, and will result in digital devices ranging from smartphones to laptops with faster response time and improved reliability. By investigating the design of energy-efficient and high-bandwidth photonic-3D NoC architectures, this proposal describes a transformative and viable approach to combine technology, algorithm and applications? research to enable building scalable multicores. The cross-cutting nature of this research will foster new research directions in several areas, spanning technology/energy-aware NoC design, novel computer architectures, and cutting-edge modeling and simulations tools for emerging technologies. This research will also play a major role in education by integrating discovery with teaching and training. Several graduate students will be directly involved with all phases of the project from which the core parts of their dissertations and theses will be derived. It will also benefit a wider audience of graduate and undergraduate students by incorporating the new research into several courses on computer architecture and parallel processing taught by the PIs. Finally, the results and findings of the proposed research will be disseminated to researchers, engineers and educators through technical publications and presentations.