SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures Optimized for Energy, Performance and Reliability

片上网络(NoC)体系结构已经成为多核和芯片多处理器(CMPS)的主流片上通信结构。然而，随着NOC架构的扩展，它们面临着严峻的挑战。当今解决优化的NoC架构设计的一个关键挑战是NoC设计者可以使用的过多的性能增强、节能和容错技术，以及必须导航的巨大设计空间，以同时降低功耗、提高可靠性、提高性能和维护服务质量。这项研究提出了一种新的跨层、横切的方法，横跨电路、体系结构、机器学习算法和应用程序，旨在设计节能、可靠和可扩展的片上网络。这项研究将产生(1)新颖的跨层设计技术，这些技术采取全面的方法来同时降低功耗，同时仍能实现片上网络的可靠性和性能目标，(2)基本了解如何使用硬件兼容的ML进行片上网络设计优化，(3)用于监控和收集网络执行期间的关键数据和关键设计参数以优化片上网络设计的软硬件技术，以及(4)将改进体系结构社区的建模和仿真工具？S设计方法用于评估可扩展的片上网络设计方法。拟议的研究在硬件架构师和机器学习科学家之间架起了一座非常重要的鸿沟，前者在电路和体系结构级别设计电源管理和容错技术，后者开发预测和优化技术。由于其交叉性质，拟议的研究有可能显著改变下一代CMPS和片上系统(SoC)的设计，在这些领域，必须做出影响功率、性能和可靠性的复杂决策。这项研究还将通过将发现与教学和培训相结合，在教育中发挥重要作用。作为拟议项目的一部分，私人投资机构致力于并将继续扩大外联活动，作出必要努力吸引和培训这一领域的少数族裔学生。

Network-on-Chip (NoC) architectures have emerged as the prevailing on-chip communication fabric for multicores and Chip Multiprocessors (CMPs). However, as NoC architectures are scaled, they face serious challenges. A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs. This research will result in (1) novel cross-layer design techniques that take a holistic approach of simultaneously reducing power consumption, while still achieving reliability and performance goals for NoCs, (2) a fundamental understanding of the use of hardware-amenable ML for NoC design optimization, (3) software and hardware techniques for monitoring and collecting critical data and key design parameters during network execution to optimize NoC design, and (4) modeling and simulation tools that will improve the architecture community?s design methodologies for evaluating scalable NoCs. The proposed research bridges a very important gap between hardware architects who design power management and fault tolerant techniques at the circuit and architecture level and machine learning scientists who develop predictive and optimization techniques. Due to its cross-cutting nature, the proposed research has the potential to significantly transform the design of next-generation CMPs and System-on-Chips (SoCs) where complex decisions have to be made that affect the power, performance and reliability. The research will also play a major role in education by integrating discovery with teaching and training. The PIs are committed and will continue to expand on outreach activities as part of the proposed project by making the necessary efforts to attract and train minority students in this field.