SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures Optimized for Energy, Performance and Reliability

SHF：中：协作研究：支持机器学习的片上网络架构，针对能源、性能和可靠性进行了优化

基本信息

批准号：
1702980
负责人：
Ahmed Louri
金额：
$ 45万
依托单位：
George Washington University
依托单位国家：
美国
项目类别：
Continuing Grant
财政年份：
2017
资助国家：
美国
起止时间：
2017-06-01 至 2023-05-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1702980&HistoricalAwards=false
关键词：
SHF Medium Collaborative Research Machine

项目摘要

Network-on-Chip (NoC) architectures have emerged as the prevailing on-chip communication fabric for multicores and Chip Multiprocessors (CMPs). However, as NoC architectures are scaled, they face serious challenges. A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs. This research will result in (1) novel cross-layer design techniques that take a holistic approach of simultaneously reducing power consumption, while still achieving reliability and performance goals for NoCs, (2) a fundamental understanding of the use of hardware-amenable ML for NoC design optimization, (3) software and hardware techniques for monitoring and collecting critical data and key design parameters during network execution to optimize NoC design, and (4) modeling and simulation tools that will improve the architecture community?s design methodologies for evaluating scalable NoCs. The proposed research bridges a very important gap between hardware architects who design power management and fault tolerant techniques at the circuit and architecture level and machine learning scientists who develop predictive and optimization techniques. Due to its cross-cutting nature, the proposed research has the potential to significantly transform the design of next-generation CMPs and System-on-Chips (SoCs) where complex decisions have to be made that affect the power, performance and reliability. The research will also play a major role in education by integrating discovery with teaching and training. The PIs are committed and will continue to expand on outreach activities as part of the proposed project by making the necessary efforts to attract and train minority students in this field.

片上网络（NOC）架构已成为用于多学院和芯片多处理器（CMP）的流行片上通信结构。但是，随着NOC架构的扩展，它们面临严重的挑战。当今解决优化的NOC体系结构设计的一个关键挑战是，可供NOC设计师使用的大量增强性能，节能和容忍度的技术以及必须导航的大型设计空间，以同时降低功率，提高可靠性，提高性能，提高性能并保持QoS。这项研究提出了一种跨越电路，体系结构，机器学习算法和应用的新的跨层，横切方法，旨在设计能效，可靠和可扩展的NOC。这项研究将导致（1）新颖的跨层设计技术，这些技术采取了同时减少功耗的整体方法，同时仍然实现了NOC的可靠性和性能目标，（2）对使用硬件无关的ML用于NOC设计的使用的基本了解，在NOC设计中使用硬件无限的ML在NOC设计中进行优化，（3）在监视和收集4个型号的构图（3）关键数据范围内（4），并收集了4个型号的设计，该模型（4）具有关键数据设计（4），该模型（4）是4个构图（4），并构成了4个构图（4），并构成了4个构图（4），并构成了4个范围的设计范围（4）设计了（4个）设计范围的设计（键入启用了纽带的设计范围）。以及将改善架构社区的设计方法的仿真工具，用于评估可扩展的NOC。拟议的研究弥合了在巡回赛和建筑级别设计电源管理和容忍技术的硬件建筑师之间的一个非常重要的差距，以及开发预测性和优化技术的机器学习科学家。由于其横切性质，拟议的研究有可能显着改变下一代CMP和芯片系统（SOC）的设计，在这些设计中必须做出复杂的决定，以影响力量，性能和可靠性。这项研究还将通过将发现与教学和培训相结合，在教育中发挥重要作用。 PIS是努力的，并将通过在该领域吸引和培训少数族裔学生的必要努力来继续扩大外展活动，作为拟议项目的一部分。

项目成果

期刊论文数量（17）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference

DOI：
10.1109/hpca53966.2022.00066
发表时间：
2022-04
期刊：
2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
影响因子：
0
作者：
Yuan Li;A. Louri;Avinash Karanth
通讯作者：
Yuan Li;A. Louri;Avinash Karanth

PIXEL: Photonic Neural Network Accelerator

DOI：
10.1109/hpca47549.2020.00046
发表时间：
2020-02
期刊：
2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)
影响因子：
0
作者：
Kyle Shiflett;Dylan Wright;Avinash Karanth;A. Louri
通讯作者：
Kyle Shiflett;Dylan Wright;Avinash Karanth;A. Louri

GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks

DOI：
10.1109/hpca51647.2021.00070
发表时间：
2021-02
期刊：
2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
影响因子：
0
作者：
Jiajun Li;A. Louri;Avinash Karanth;Razvan C. Bunescu
通讯作者：
Jiajun Li;A. Louri;Avinash Karanth;Razvan C. Bunescu

SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-based Accelerator with Photonic Interconnects for CNN Inference