SHF: Small: Collaborative Research: A Holistic Design Methodology for Fault-Tolerant and Robust Network-on-Chips (NoCs) Architectures

缩小到纳米级的技术有助于晶体管的发展，使多核架构成为利用并行性和提高性能的节能方法。因此，设计低延迟、高带宽、高能效和可靠的片上网络（NoC）被证明是实现未来芯片性能潜力的最关键挑战之一。虽然多核技术促进了巨大的集成能力，但积极的晶体管缩放也导致了器件和电路可靠性的稳步下降。器件磨损的增加（由于负偏置温度不稳定性（NBTI）、电迁移（EM）和热载流子注入（HCI））加剧了晶体管可靠性的下降，从而导致故障（永久性和瞬时性）和硬件故障的显著增加。由于NoC基板内出现故障，多核芯片在从故障中恢复时面临过度延迟和增加的功耗。虽然NoC可靠性研究在路由器间和路由器内水平上取得了重大进展，但仍然缺乏一种整体设计方法，该方法涵盖了整个NoC架构的可靠性，从设备磨损到链路和路由器，到路由协议，再到应用程序，以一种连贯的方式，本项目将开发一种整体设计方法，解决整个NoC通信基础设施的可靠性问题（设备、链路、路由器、路由算法和拓扑），同时最小化能量足迹、减少面积开销并且仅略微影响性能。为了实现我们的目标，提高链路故障恢复，这个项目将开发技术，以最大限度地利用路由器间的链路，以最小的功率和面积开销。对于路由器，本项目将提出路由器内部可靠性技术，其目标是最大限度地提高硬件利用率，减少冗余和面积开销，并最大限度地减少路由器管道延迟。此外，该项目开发的磨损均衡技术将提高NoC的可靠性和芯片的寿命。最后，所提出的技术将通过开发故障模型注入到片上网络进行评估，并通过广泛的建模和仿真评估故障覆盖率，性能退化和能源效率。整个NoC架构的整体设计方法和该项目开发的可靠性技术将对下一代多核和片上系统（SoC）架构产生积极影响，提高能源效率，性能和对硬故障和软错误的鲁棒性。该项目将在教育方面发挥重要作用，将发现与教学和培训相结合，吸引和培训这一领域的少数民族学生。

Technology scaling down to the nanometer regime has aided the growth in transistors that have made multi-core architectures a power-efficient approach to harnessing parallelism and improving performance. Consequently, the design of low latency, high bandwidth, power-efficient and reliable Network-on-Chips (NoCs) is proving to be one of the most critical challenges to achieving the performance potential of future chips. While multicores are facilitating an enormous integration capacity, aggressive transistor scaling has also led to a steady degradation of the device and circuit reliability. Increased device wear-out (due to negative-bias temperature instability (NBTI), electro migration (EM) and hot carrier injection (HCI)) has exacerbated the waning reliability of transistors, thereby resulting in a significant increase in faults (both permanent and transient), and hardware failures. As faults manifest within the NoC substrate, multicore chips are faced with excessive delays and increased power consumption while recovering from the fault. While NoC reliability research has made significant strides at inter- and intra-router levels, there is still a lack of a holistic design approach covering the reliability of the entire NoC architecture, from device wear-out, to links and routers, to routing protocols, to applications in a cohesive manner.This project will develop a holistic design methodology that addresses the reliability of the entire NoC communication infrastructure (device, links, routers, routing algorithms, and topology) while minimizing energy footprint, reducing the area overhead and only marginally impacting performance. To achieve our goal of improving link fault-recovery, this project will develop techniques to maximize the utilization of the inter-router links with minimum power and area overhead. For the router, this project will propose intra-router reliability techniques with the goals of maximizing hardware utilization, reducing redundancy and area overhead, and minimizing router pipeline latency. Further, wear-leveling techniques developed by this project will improve the reliability of NoCs and the lifetime of the chip. Finally, the proposed techniques will be evaluated by developing fault models that are injected into the NoC and evaluate the fault coverage, performance degradation and energy efficiency through extensive modeling and simulation. The holistic design methodology spanning the entire NoC architecture and the reliability techniques developed from this project will positively impact the next generation multi-core and System-on-Chip (SoC) architectures with improvements in energy efficiency, performance and robustness to hard faults and soft errors. This project will play a major role in education by integrating discovery with teaching and training, and by attracting and training minority students in this field.