SHF: Small: Collaborative Research: A Holistic Design Methodology for Fault-Tolerant and Robust Network-on-Chips (NoCs) Architectures

缩小到纳米级的技术有助于晶体管的增长，这些晶体管使多核架构成为利用并行性和提高性能的一种节能方法。因此，设计低延迟、高带宽、高功耗和可靠的片上网络(NoCs)被证明是实现未来芯片性能潜力的最关键挑战之一。虽然多核有助于实现巨大的集成容量，但激进的晶体管扩展也导致了设备和电路可靠性的稳步下降。由于负偏压温度不稳定性(NBTI)、电迁移(EM)和热载流子注入(HCI)导致的器件损耗增加，加剧了晶体管可靠性的下降，从而导致故障(永久和瞬时故障)和硬件故障的显著增加。由于NOC基板中的故障明显，多核芯片在从故障中恢复时面临过多的延迟和增加的功耗。虽然NoC可靠性研究已经在路由器间和路由器内级别取得了重大进展，但仍然缺乏涵盖整个NoC体系结构可靠性的整体设计方法，从设备损耗到链路和路由器，再到路由协议，再到应用程序。该项目将开发一种整体设计方法，以解决整个NoC通信基础设施(设备、链路、路由器、路由算法和拓扑)的可靠性，同时最大限度地减少能源消耗，减少区域开销，并且仅对性能产生轻微影响。为了实现提高链路故障恢复的目标，该项目将开发以最小的功率和区域开销最大化路由器间链路利用率的技术。对于路由器，本项目将提出路由器内可靠性技术，目标是最大化硬件利用率，减少冗余和区域开销，并最大限度地减少路由器管道延迟。此外，本项目开发的磨损均衡技术将提高片上网络的可靠性和芯片的寿命。最后，通过建立注入片上网络的故障模型来评估所提出的技术，并通过广泛的建模和仿真来评估故障覆盖率、性能降级和能量效率。覆盖整个片上网络架构的整体设计方法和从该项目开发的可靠性技术将对下一代多核和片上系统(SoC)架构产生积极影响，提高能效、性能和对硬故障和软错误的稳健性。该项目将通过将发现与教学和培训相结合，并通过吸引和培训这一领域的少数民族学生，在教育中发挥重要作用。

Technology scaling down to the nanometer regime has aided the growth in transistors that have made multi-core architectures a power-efficient approach to harnessing parallelism and improving performance. Consequently, the design of low latency, high bandwidth, power-efficient and reliable Network-on-Chips (NoCs) is proving to be one of the most critical challenges to achieving the performance potential of future chips. While multicores are facilitating an enormous integration capacity, aggressive transistor scaling has also led to a steady degradation of the device and circuit reliability. Increased device wear-out (due to negative-bias temperature instability (NBTI), electro migration (EM) and hot carrier injection (HCI)) has exacerbated the waning reliability of transistors, thereby resulting in a significant increase in faults (both permanent and transient), and hardware failures. As faults manifest within the NoC substrate, multicore chips are faced with excessive delays and increased power consumption while recovering from the fault. While NoC reliability research has made significant strides at inter- and intra-router levels, there is still a lack of a holistic design approach covering the reliability of the entire NoC architecture, from device wear-out, to links and routers, to routing protocols, to applications in a cohesive manner.This project will develop a holistic design methodology that addresses the reliability of the entire NoC communication infrastructure (device, links, routers, routing algorithms, and topology) while minimizing energy footprint, reducing the area overhead and only marginally impacting performance. To achieve our goal of improving link fault-recovery, this project will develop techniques to maximize the utilization of the inter-router links with minimum power and area overhead. For the router, this project will propose intra-router reliability techniques with the goals of maximizing hardware utilization, reducing redundancy and area overhead, and minimizing router pipeline latency. Further, wear-leveling techniques developed by this project will improve the reliability of NoCs and the lifetime of the chip. Finally, the proposed techniques will be evaluated by developing fault models that are injected into the NoC and evaluate the fault coverage, performance degradation and energy efficiency through extensive modeling and simulation. The holistic design methodology spanning the entire NoC architecture and the reliability techniques developed from this project will positively impact the next generation multi-core and System-on-Chip (SoC) architectures with improvements in energy efficiency, performance and robustness to hard faults and soft errors. This project will play a major role in education by integrating discovery with teaching and training, and by attracting and training minority students in this field.