Collaborative Research: SHF: Medium: EPIC: Exploiting Photonic Interconnects for Resilient Data Communication and Acceleration in Energy-Efficient Chiplet-based Architectures

在基于芯片的架构中，连接核心、加速器和存储器的片上通信结构目前消耗大量的功率，必须设计成不仅提供足够的连接和性能，而且还必须非常节能和可扩展，以满足未来的计算需求。由于硅光子学具有更好的每瓦性能和更高的带宽密度，它有可能缓解一些片上通信问题。当今解决这一设计挑战的一个关键问题是，由于交通模式的时空波动，昂贵的硅光子技术未得到充分利用。为了使硅光子学实用和可行，重新利用未充分利用的资源进行计算可以加快应用程序的执行速度，并提供急需的节能数据传输。本文的研究对基于芯片的异构多核架构的持续发展具有重要意义。这是一项有组织的工作，将技术、架构、应用和机器学习的最新进展结合到一个有前途的集成方法中，该方法将解决未来计算系统最关键的挑战之一，即设计下一代通信结构，用于高性能、节能和可扩展的异构架构，具有更高的功能和灵活性。所有的研究成果和模拟工具包将通过会议和期刊出版物以及一个专门的网站向社区传播。这项研究还将通过将发现与教学和培训结合起来，在教育方面发挥重要作用。这项研究将继续扩大外联活动和扩大对计算机的参与，作出必要的努力，吸引和培训这一领域代表性不足的学生和少数民族学生。本研究将设计一种新颖的、双重用途的光子结构，它不仅可以实现高效节能和可扩展的异质多核片上通信，还可以作为一种经济高效的高性能神经网络加速器，用于各种应用。该思想的核心是：(1)在高网络负载时在核心和加速器之间提供高带宽和高能效的数据传输；(2)在低网络负载时将关键加速器功能卸载到同一网络，以最大限度地利用资源并加快计算速度，从而实现光子结构的双重用途。预计精心编排数据通信（片内和片外），在通信和计算之间共享硬件资源以及实现光神经计算的综合效果将为下一代异构基于芯片的架构提供极其节能和可扩展的平台。本研究将产生(1)可同时用于计算和通信的新型光子体系结构；(2)对实现加速器功能的光子计算的基本理解；(3)光子体系结构的硬件技术，以动态适应应用需求，从而最大化功率效率并提高弹性。(4)概念验证和开源工具，它们将扩展和增强计算机体系结构社区在这一关键领域的研究能力。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The on-chip communication fabric connecting the cores, accelerators and the memory in chiplet-based architectures consumes a significant amount of power today and must be designed to not only provide adequate connectivity and performance, but also be very energy efficient and scalable, to satisfy future computing demands. Silicon photonics has the potential to alleviate some of the on-chip communication problems thanks to better performance-per-watt and higher bandwidth density. A key issue in addressing this design challenge today is the under-utilization of the expensive silicon photonics technology due to temporal and spatial fluctuation of traffic patterns. To make silicon photonics practical and viable, re-purposing the under-utilized resources for computation can speed up application execution and provide much-needed energy-efficient data transfers. The proposed research is timely and vital for the continued growth of chiplet-based heterogeneous manycore architectures. It is an organized effort that combines recent advances in technology, architecture, application, and machine learning into a promising integrated approach that will tackle one of the most critical challenges of computing systems of the future, namely the design of next-generation communication fabrics for high-performance, energy-efficient and scalable heterogeneous architectures with much-increased functionality and flexibility. All the research findings and simulation toolkits will be disseminated to the community via conference and journal publications, and a dedicated website. The research will also play a major role in education by integrating discovery with teaching and training. This research will continue to expand on outreach activities and broadening participation in computing by making the necessary efforts to attract and train underrepresented and minority students in this field. This research will design a novel, dual-purpose photonic fabric that will not only enable power-efficient and scalable on-chip communications for heterogeneous multicores but will also function as a cost-efficient and high-performance neural network accelerator for diverse applications. The crux of the idea is to: (1) provide high-bandwidth and power-efficient data transfer between cores and accelerators during high network load, and (2) off-load key accelerator functions to the same network during low network load to maximize resource utilization and speedup computation, hence the dual-purpose nature of the photonic fabric. It is expected that the combined effects of meticulously orchestrating data communication (on-chip and off-chip), sharing hardware resources between communication and computation, and implementing optical neural computations will provide an extremely power-efficient and scalable platform for next-generation heterogeneous chiplet-based architectures. This research will result in (1) novel photonic architectures that can be leveraged for computing and communication simultaneously, (2) a fundamental understanding of photonic computation for implementing accelerator functions, (3) hardware techniques for photonic architectures to dynamically adapt to application demands to maximize the power-efficiency and improve resiliency, and (4) proof-of-concept and open-source tools that will expand and enhance the research capabilities of the computer architecture community in this critical area.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.