CAREER: New Directions in Functional Verification of Heterogeneous Multicore Architectures

职业：异构多核架构功能验证的新方向

• 批准号: 0746261
• 负责人: Prabhat Mishra
• 金额: $ 32万
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-06-01 至 2014-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0746261&HistoricalAwards=false
• 关键词: CAREER; New; Directions; Functional; Verification

Functional verification is widely acknowledged as a major bottleneck in System-on-Chip (SOC) design methodology. The verification complexity is expected to increase further due to the combined effects of increasing design complexity and recent paradigm shift from single processor SOC designs to heterogeneous multicore SOC (HMSOC) architectures, which are expected to receive wide use in future embedded systems. A significant bottleneck in the verification of HMSOC architectures is the lack of a "golden reference model" and associated design automation techniques. The central objective of this project is to develop automated tools and techniques to drastically reduce the functional verification effort for future embedded systems. The core of this NSF CAREER research is the synergistic integration of three innovative concepts to enable top-down validation using a single specification: i) a unified specification language that can capture a wide variety of multicore SOC architectures, ii) validation of static and dynamic behaviors of the specified architecture, and iii) coverage-directed functional test generation for implementation validation using a combination of simulation-based techniques and formal methods. This integration has potential for substantially advancing the state of the art in verification of complex and heterogeneous embedded systems. The development of top-down validation methodology can drastically reduce the overall verification effort and enable generation of efficient and cost-effective embedded systems -- low cost everyday appliances for the public and improved accuracy for safety-critical devices. This project seeks broad educational impact and integration of research and education through two venues: i) development of embedded systems courses for undergraduate and graduate students, and ii) involvement of undergraduate students and outreach through UF University Scholars and NSF-sponsored SEAGEP programs.

功能验证是系统级芯片（SOC）设计中的一个重要瓶颈。由于设计复杂度的增加和最近从单处理器SOC设计到异构多核SOC（HMSOC）架构的范式转变的综合影响，预计验证复杂度将进一步增加，这有望在未来的嵌入式系统中得到广泛使用。HMSOC体系结构验证的一个重要瓶颈是缺乏“黄金参考模型”和相关的设计自动化技术。该项目的中心目标是开发自动化工具和技术，以大大减少未来嵌入式系统的功能验证工作。这项NSF CAREER研究的核心是三个创新概念的协同集成，以使用单一规范实现自上而下的验证：i）可以捕获各种多核SOC架构的统一规范语言，ii）验证指定架构的静态和动态行为，以及iii）使用基于模拟的技术和形式化方法的组合的用于实现验证的覆盖率导向的功能测试生成。这种集成有可能大大推进先进的复杂和异构嵌入式系统的验证。自上而下的验证方法的开发可以大大减少整体验证工作，并能够生成高效且具有成本效益的嵌入式系统-为公众提供低成本的日常设备，并提高安全关键设备的准确性。该项目旨在通过两个地点广泛的教育影响和研究与教育的整合：i）为本科生和研究生开发嵌入式系统课程，ii）通过UF大学学者和NSF赞助的SEAGEP计划参与本科生和外联。