CAREER: New Directions in Functional Verification of Heterogeneous Multicore Architectures

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Functional verification is widely acknowledged as a major bottleneck in System-on-Chip (SOC) design methodology. The verification complexity is expected to increase further due to the combined effects of increasing design complexity and recent paradigm shift from single processor SOC designs to heterogeneous multicore SOC (HMSOC) architectures, which are expected to receive wide use in future embedded systems. A significant bottleneck in the verification of HMSOC architectures is the lack of a "golden reference model" and associated design automation techniques. The central objective of this project is to develop automated tools and techniques to drastically reduce the functional verification effort for future embedded systems. The core of this NSF CAREER research is the synergistic integration of three innovative concepts to enable top-down validation using a single specification: i) a unified specification language that can capture a wide variety of multicore SOC architectures, ii) validation of static and dynamic behaviors of the specified architecture, and iii) coverage-directed functional test generation for implementation validation using a combination of simulation-based techniques and formal methods. This integration has potential for substantially advancing the state of the art in verification of complex and heterogeneous embedded systems. The development of top-down validation methodology can drastically reduce the overall verification effort and enable generation of efficient and cost-effective embedded systems -- low cost everyday appliances for the public and improved accuracy for safety-critical devices. This project seeks broad educational impact and integration of research and education through two venues: i) development of embedded systems courses for undergraduate and graduate students, and ii) involvement of undergraduate students and outreach through UF University Scholars and NSF-sponsored SEAGEP programs.