SHF: Small: Collaborative Research: Testing and Design-for-Testability Solutions for 3D Stacked Integrated Circuits

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Three-dimensional stacked integrated circuits (3D SICs) promise to overcome barriers in interconnect scaling, thereby offering an opportunity to get higher performance using CMOS technology. This collaborative project between Duke University and Pennsylvania State University is focused on test and design-for-testability (DFT) solutions for 3D SICs. Topics being investigated include: (i) fault modeling and test generation, where the goal is to develop new fault models and test generation methods that can effectively target defects unique to 3D SICs; (ii) DFT infrastructure, optimization techniques for test access, and test scheduling methods for pre-bond test and post-bond test; (iii) Test economics and a cost-analysis framework, where test cost is being incorporated into cost models for 3D IC design and fabrication. This project will facilitate further advances in 3D integration and wider adoption of this emerging technology by the semiconductor industry. Innovations in test methods, DFT, and cost modeling will therefore have a transformative impact on the way in which semiconductor chips are designed and fabricated. Undergraduate and graduate students involved in this research will be trained for the next-generation semiconductor industry workforce. Tools and techniques developed in this research will be used in teaching existing courses and developing new courses. A virtual classroom through web delivery will facilitate collaborative lectures originating from Duke and Penn State. The PIs will make tools available through the web for use by other educators, researchers, and industry practitioners. At Duke, the PI will mentor undergraduate students in collaboration with the Associate Dean for Education and Outreach Programs in the Pratt School of Engineering, and generate excitement among high-school students at the North Carolina School of Science and Mathematics.