SHF: Small: Hardware-Software Co-Design for Next Generation Packet Forwarding Engines

SHF：小型：下一代数据包转发引擎的软硬件协同设计

• 批准号: 1116781
• 负责人: Viktor Prasanna
• 金额: $ 39.99万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116781&HistoricalAwards=false
• 关键词: SHF; Small; Hardware; Software; Co

The Internet backbone, including both core and edge routers, is becoming more flexible, scalable and programmable to enable future innovations in the next generation Internet. While the functionality of Internet routers evolves, the performance remains a major concern for real-life deployment. Traditionally, core routers have been designed using throughput as a key performance metric. While the throughput requirements continue to grow, peak power and total energy dissipated have emerged as additional critical considerations in the design of core routers as well as in other network equipment. Although ternary content addressable memories (TCAMs) have been widely used for packet forwarding, they have poor power performance. This work studies the use of low-power memory technology such as the static random access memory (SRAM) combined with field-programmable gate arrays (FPGAs) / application-specific integrated circuits (ASICs) to develop high-throughput and power-efficient solutions for various packet forwardingengines including IP lookup, router virtualization, packet classification and flexible flow processing (e.g., OpenFlow). Packet forwarding engines in next generation routers and switches are designed using a hardware-software co-design framework. Based on this framework, novel architectures and algorithms are developed using power (including energy) as a key performance metric in addition to throughput. Specifically, to bridge the gap between software and hardware development, high-level power-performance models for hardware implementations of packet forwarding engines are developed and validated. These models facilitate design of various heuristics for power-efficient algorithms and architectures for virtualized IP lookup, multi-field packet classification and flexible flow processing. Instead of the highly popular TCAM based solutions, this work focuses on SRAM-based parallel and pipeline architectures. Novel techniques including partitioning, clock gating, power-aware data structure design and power-aware load balancing are studied to simultaneously increase throughput and reduce power and/or energy dissipation

包括核心和边缘路由器在内的互联网骨干正变得更加灵活、可扩展和可编程，以实现下一代互联网的未来创新。虽然互联网路由器的功能不断发展，但性能仍然是实际部署的主要关注点。传统上，核心路由器的设计使用吞吐量作为关键性能指标。在吞吐量需求持续增长的同时，峰值功率和总能耗已成为核心路由器以及其他网络设备设计中的额外关键考虑因素。虽然三元内容可寻址存储器（TCAMs）被广泛用于数据包转发，但其功耗性能较差。这项工作研究了使用低功耗存储器技术，如静态随机存取存储器（SRAM）与现场可编程门阵列(fpga) /专用集成电路（asic）相结合，为各种数据包转发引擎开发高吞吐量和节能的解决方案，包括IP查找，路由器虚拟化，数据包分类和灵活的流处理（例如，OpenFlow）。下一代路由器和交换机中的包转发引擎采用软硬件协同设计框架进行设计。在此框架的基础上，除了吞吐量之外，还使用功率（包括能量）作为关键性能指标，开发了新的架构和算法。具体来说，为了弥合软件和硬件开发之间的差距，开发并验证了数据包转发引擎硬件实现的高级功率性能模型。这些模型有助于为高效节能算法和架构设计各种启发式算法，用于虚拟IP查找，多字段数据包分类和灵活的流处理。与非常流行的基于TCAM的解决方案不同，这项工作侧重于基于sram的并行和管道架构。研究了包括分区、时钟门控、功率感知数据结构设计和功率感知负载平衡在内的新技术，以同时提高吞吐量并降低功耗和/或能耗