SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures for Optimized Energy, Performance and Reliability

片上网络（NoC）架构已经成为多核和片上多处理器（CMP）的主流片上通信结构。然而，随着NoC架构的规模化，它们面临着严峻的挑战。当今解决优化NoC架构设计的一个关键挑战是NoC设计人员可用的大量性能增强、节能和容错技术，以及必须导航以同时降低功耗、提高可靠性、提高性能和保持QoS的大设计空间。该研究提出了一种新的跨层、跨领域的方法，涵盖电路、架构、机器学习算法和应用，旨在设计节能、可靠和可扩展的NoCs。这项研究将导致（1）新的跨层设计技术，采用整体方法，同时降低功耗，同时仍然实现NoC的可靠性和性能目标，（2）对使用硬件兼容ML进行NoC设计优化的基本理解，（3）用于在网络执行期间监视和收集关键数据和关键设计参数以优化NoC设计的软件和硬件技术，以及（4）建模和仿真工具，这将改善体系结构社区的设计方法，以评估可扩展的NoCs。拟议的研究弥合了在电路和架构级别设计电源管理和容错技术的硬件架构师与开发预测和优化技术的机器学习科学家之间非常重要的差距。由于其跨领域的性质，拟议的研究有可能显着改变下一代CMP和片上系统（SoC）的设计，其中必须做出影响功率，性能和可靠性的复杂决策。该研究还将通过将发现与教学和培训相结合，在教育中发挥重要作用。作为拟议项目的一部分，项目执行人承诺并将继续扩大外联活动，作出必要的努力，吸引和培训这一领域的少数民族学生。

Network-on-Chip (NoC) architectures have emerged as the prevailing on-chip communication fabric for multicores and Chip Multiprocessors (CMPs). However, as NoC architectures are scaled, they face serious challenges. A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs. This research will result in (1) novel cross-layer design techniques that take a holistic approach of simultaneously reducing power consumption, while still achieving reliability and performance goals for NoCs, (2) a fundamental understanding of the use of hardware-amenable ML for NoC design optimization, (3) software and hardware techniques for monitoring and collecting critical data and key design parameters during network execution to optimize NoC design, and (4) modeling and simulation tools that will improve the architecture community's design methodologies for evaluating scalable NoCs. The proposed research bridges a very important gap between hardware architects who design power management and fault tolerant techniques at the circuit and architecture level and machine learning scientists who develop predictive and optimization techniques. Due to its cross-cutting nature, the proposed research has the potential to significantly transform the design of next-generation CMPs and System-on-Chips (SoCs) where complex decisions have to be made that affect the power, performance and reliability. The research will also play a major role in education by integrating discovery with teaching and training. The PIs are committed and will continue to expand on outreach activities as part of the proposed project by making the necessary efforts to attract and train minority students in this field.