SHF: Small: Collaborative Research: Power-Efficient and Reliable 3D Stacked Reconfigurable Photonic Network-on-Chips for Scalable Multicore Architectures

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As power dissipation on a single-chip is increasing at an alarming rate due to massive integration of digital circuits, multicore design has become the only technique to scale performance. Multicores with tens to hundreds of cores are already available in the marketplace and future projections call for thousands of cores on the chip. To achieve scalable computing performance from the multicores, the communication between cores should also scale in bandwidth while significantly reducing the power consumption. Scaling the performance of the on-chip communication fabric, called the Network-on-Chip (NoC), has proven to be a significant challenge with traditional metallic interconnects due to fundamental signaling issues such as power dissipation, electromagnetic interference, crosstalk and reflections. Several studies and roadmaps have indicated that disruptive technology solutions such as photonics have the potential to alleviate the critical bandwidth, power and latency challenges of future multicores. This research seeks to exploit the unique advantages of photonic interconnects and 3D stacking technologies to develop scalable, energy-efficient, bandwidth-reconfigurable and reliable NoCs for future multicores. There are three goals of the proposed research: first, it will investigate and develop 3D stacked photonic NoC architectures and topologies that maximize performance and improve energy-efficiency; second, it will develop runtime reconfiguration techniques that can adapt the network to the communication needs of the application, thereby improving performance on a per-application basis; and third, it will result in an extensive modeling and simulation framework to be used for designing and validating future photonic NoC architectures.This research has far reaching broader impacts. This research is uniquely positioned to leverage two emerging technologies namely photonics and 3D stacking to meet the multicore challenge and will significantly benefit society. The proposed research is essential to continue the growth of computing performance that our society depends upon, and will result in digital devices ranging from smartphones to laptops with faster response time and improved reliability. By investigating the design of energy-efficient and high-bandwidth photonic-3D NoC architectures, this proposal describes a transformative and viable approach to combine technology, algorithm and applications' research to enable building scalable multicores. The cross-cutting nature of this research will foster new research directions in several areas, spanning technology/energy-aware NoC design, novel computer architectures, and cutting-edge modeling and simulations tools for emerging technologies. This research will also play a major role in education by integrating discovery with teaching and training. Several graduate students will be directly involved with all phases of the project from which the core parts of their dissertations and theses will be derived. It will also benefit a wider audience of graduate and undergraduate students by incorporating the new research into several courses on computer architecture and parallel processing taught by the PIs. Finally, the results and findings of the proposed research will be disseminated to researchers, engineers and educators through technical publications and presentations.