SHF: Small: Collaborative Research: Design of Power and Area Efficient, Fault-tolerant Network-on-Chip Circuits and Architectures

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"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."The proliferation of multiple cores on the same die has given rise to communication-centric systems, wherein the design of the interconnection network has become extremely important. To address the growing wire delay problems and improve performance in CMP architectures, a growing number of multi-core designs have adopted a more flexible, scalable, packet-switched architecture called Network-on-Chip (NoC). Of the several challenges facing current NoC designs, the three prominent ones are power dissipation, die area, and overall performance. In this research, we propose to develop energy-efficient, area-efficient, high-performance, and fault-tolerant NoCs by exploiting innovative technological (circuit) optimizations and architectural design space. On the technology side, we will develop and design novel circuit techniques that will achieve significant power savings, fault-tolerance and considerable reduction in area requirements. On the architectural side, we will develop novel NoC designs that incorporate the proposed circuit design techniques and further improve network performance. This research is an organized effort that will combine circuit analysis, architecture study, performance evaluation and design synthesis. We will develop a comprehensive NoC design platform which will analyze the trade-offs among various parameters of interest ? power, area and performance.The success of this research is likely to have a significant impact on the design of NoC architectures for CMPs. The proposed research will tackle some of the major limitations of NoC design, namely power consumption and reliability, and will make significant advances in understanding the interplay between performance, energy, and reliability for NoC architectures. Realistic solutions to these problems will provide the ability to continue the improvements in computational performance that the information technology sector of our economy depends on. This multi-disciplinary research will also play a major role in education by integrating discovery with teaching and training.