SHF: Small: Collaborative Research: Design of Power and Area Efficient, Fault-tolerant Network-on-Chip Circuits and Architectures

SHF：小型：协作研究：功耗和面积高效、容错片上网络电路和架构的设计

• 批准号: 0915418
• 负责人: Avinash Karanth
• 金额: $ 13.44万
• 依托单位: Ohio University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-08-01 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0915418&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Design

"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."The proliferation of multiple cores on the same die has given rise to communication-centric systems, wherein the design of the interconnection network has become extremely important. To address the growing wire delay problems and improve performance in CMP architectures, a growing number of multi-core designs have adopted a more flexible, scalable, packet-switched architecture called Network-on-Chip (NoC). Of the several challenges facing current NoC designs, the three prominent ones are power dissipation, die area, and overall performance. In this research, we propose to develop energy-efficient, area-efficient, high-performance, and fault-tolerant NoCs by exploiting innovative technological (circuit) optimizations and architectural design space. On the technology side, we will develop and design novel circuit techniques that will achieve significant power savings, fault-tolerance and considerable reduction in area requirements. On the architectural side, we will develop novel NoC designs that incorporate the proposed circuit design techniques and further improve network performance. This research is an organized effort that will combine circuit analysis, architecture study, performance evaluation and design synthesis. We will develop a comprehensive NoC design platform which will analyze the trade-offs among various parameters of interest ? power, area and performance.The success of this research is likely to have a significant impact on the design of NoC architectures for CMPs. The proposed research will tackle some of the major limitations of NoC design, namely power consumption and reliability, and will make significant advances in understanding the interplay between performance, energy, and reliability for NoC architectures. Realistic solutions to these problems will provide the ability to continue the improvements in computational performance that the information technology sector of our economy depends on. This multi-disciplinary research will also play a major role in education by integrating discovery with teaching and training.

“该奖项是根据2009年美国复苏和再投资法案（公法111-5）资助的。“同一芯片上多个内核的激增催生了以通信为中心的系统，其中互连网络的设计变得极其重要。为了解决CMP架构中日益严重的线延迟问题并提高性能，越来越多的多核设计采用了一种更灵活、可扩展的分组交换架构，称为片上网络（NoC）。在当前NoC设计面临的几个挑战中，三个突出的挑战是功耗、管芯面积和整体性能。在这项研究中，我们建议开发节能，面积有效，高性能和容错的NoCs，通过利用创新的技术（电路）优化和架构设计空间。在技术方面，我们将开发和设计新颖的电路技术，以实现显著的节能、容错和大幅减少面积要求。在架构方面，我们将开发新的NoC设计，将所提出的电路设计技术，并进一步提高网络性能。本研究将联合收割机电路分析、结构研究、性能评估和设计综合有机地结合在一起。我们将开发一个全面的片上网络设计平台，将分析利益的各种参数之间的权衡？功率、面积和性能。这项研究的成功可能会对用于CMP的NoC架构的设计产生重大影响。拟议的研究将解决NoC设计的一些主要限制，即功耗和可靠性，并将在理解NoC架构的性能，能源和可靠性之间的相互作用方面取得重大进展。这些问题的现实解决方案将提供继续提高计算性能的能力，这是我们经济中信息技术部门所依赖的。这种多学科研究也将通过将发现与教学和培训相结合，在教育中发挥重要作用。