CAREER: Design of Reconfigurable Power and Area-Efficient Nanophotonic Architectures for Future Multi-cores

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As the number of cores increases on the same die, computer architects and system designers have focused their attention to the on-chip network that is used for communication between the cores. Two of the major problems facing on-chip architectures are excessive power dissipation and reduced network performance. One approach to extend the performance of future multi-cores is to integrate new technologies, such as nano-photonics into the electronic design flow. Nano-photonics offers a scalable, low power per bit and a high- performance technology solution to current electrical signaling and interconnect bottlenecks. This research seeks to exploit this emerging field of nano-photonics and design reconfigurable, energy-efficient and high- performance on-chip architectures and switching interconnects. The goal of this research is to develop interconnects that can dynamically tune to the application and regulate power and bandwidth without system intervention. The proposed research will have a significant impact on the design of future multi-cores using nano-photonics. The proposed research will make advances in the understanding of the interplay between performance, energy, hardware complexity and reconfigurability. This research will also play a major role in education by integrating research with teaching and training. The educational goal of this multi-disciplinary and multi-faceted proposed research is to expose undergraduate and graduate students to diverse technological advancements with an emphasis on critical analysis and reasoning to overcome limitations of current technologies. Finally, the results and findings of the proposed research will be disseminated to researchers, engineers and educators through technical publications and presentations.