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SHF: Small: Greybox Computing: An Associative Computing Methodology with Instruction Directed Power and Clock Management

SHF: Small: Greybox Computing: An Associative Computing Methodology with Instruction Directed Power and Clock Management
SHF:小型:灰盒计算:具有指令导向电源和时钟管理的关联计算方法
批准号:
1618065
负责人:
Jie Gu
金额:
$45.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2016
资助国家:
美国
项目状态:
已结题
起止时间:
2016-07-01 至 2021-06-30

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中文摘要
翻译
能源消耗已经成为许多新兴应用的瓶颈,如可穿戴电子设备和生物医学设备。传统的低功耗设计方法已经达到了它的极限,受到性能和功耗之间的根本权衡。鉴于硬件设计和软件开发通常是分开进行的,并将彼此视为黑箱,该项目的目标是创建一种“灰箱”方法,在这种方法中,来自微处理器硬件设计的信息对更高级别的软件编译器可见,反之亦然。来自设计空间不同层的附加信息可用于建立基于近年来开发的先进功率和时钟管理电路的实时功率优化技术。通过打破传统设计空间的边界,有可能实现传统方案无法实现的显著节能。该项目提出的灰箱计算方法可以克服现有低功耗技术的局限性,提供一种基于硬件和软件联合优化的新设计范式。该项目将产生实现超节能的几项关键使能技术,包括(1)软件指令与硬件性能之间的全面关联映射,(2)高效电源和时钟管理电路的设计,(3)硬件和软件协同校准方案。该项目寻求开发一种新的低功耗系统设计范例,将在依赖电池供电或能量回收电子设备的广泛应用中产生深远的积极影响。该项目促进了一种跨学科的协作设计方法,这可能会对当前计算机设计的发展流程产生重大影响。该项目还包括通过研究生培训、课程开发和讲习班组织将研究与教育相结合的计划。在该项目的启发下开展的外联活动将鼓励人数不足的学生攻读研究生课程。
英文摘要
Energy consumption has become the bottleneck for many emerging applications such as wearable electronics and biomedical devices. The conventional low power design methodology has reached its limitation, bounded by the fundamental tradeoff of performance and power. Given that hardware design and software development are conventionally performed separately and treat each other as blackboxes, this project aims at creating a "greybox" methodology where the information from hardware design of a microprocessor are visible to the higher level software compilers and vice versa. The additional information from different layers of the design space can be used to establish a real-time power optimization technique based on advanced power and clock management circuitry developed in recent years. By breaking the boundary of the traditional design space, it is possible to achieve significant energy savings that are beyond the reach of conventional schemes. The "greybox computing" methodology proposed in this project can overcome the limitations of existing low power technology and provide a new design paradigm based on joint hardware and software optimization. The proposed project will yield several key enabling techniques to achieve ultra-energy saving including (1) a comprehensive associative mapping between software instruction and hardware performance, (2) high efficient power and clock management circuitry design, (3) hardware and software collaborative calibration scheme. This project seeks to develop a new paradigm for low-power system design that would have profound positive impact in a wide range of applications that rely on battery powered or energy scavenging electronics. The project promotes an interdisciplinary collaborative design methodology that could create strong impact on the development flow of current computer design. The project also includes plans for integrating research with education through graduate student training, course development and workshop organization. Outreach activities inspired by this project will encourage underrepresented students to pursue graduate studies.
期刊论文(10)
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科研奖励(0)
会议论文
A 0.3–0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications
具有 2GHz 谐振开关功能的 0.3–0.86V 全集成降压稳压器,适用于超低功耗应用
DOI: 10.23919/vlsic.2017.8008485
发表时间: 2017
期刊: Symposium on VLSI Circuits
影响因子: --
作者: [Jia, Tianyu, Gu, Jie]
通讯作者: Gu, Jie
Compiler-guided instruction-level clock scheduling for timing speculative processors
用于定时推测处理器的编译器引导指令级时钟调度
DOI: 10.1145/3195970.3196013
发表时间: 2018
期刊: Design Automation Conference
影响因子: --
作者: [Fan, Yuanbo, Jia, Tianyu, Gu, Jie, Campanoni, Simone, Joseph, Russ]
通讯作者: Joseph, Russ
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications
基于全集成 LC 振荡器的降压稳压器,具有适用于低功耗应用的自主谐振开关
DOI: 10.1109/asscc.2018.8579285
发表时间: 2018
期刊: Asian Solid-State Circuit Conference
影响因子: --
作者: [Jia, Tianyu, Gu, Jie]
通讯作者: Gu, Jie
A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications
适用于低功耗应用的具有 2GHz 谐振开关的完全集成降压稳压器
DOI: 10.1109/jssc.2018.2840513
发表时间: 2018
期刊: IEEE Journal of Solid-State Circuits
影响因子: 5.4
作者: [Jia, Tianyu, Gu, Jie]
通讯作者: Gu, Jie
10
    Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications
    • 批准号:
      2318807
    • 项目类别:
      Standard Grant
    • 资助金额:
      $38.5万
    • 财政年份:
      2023
    • 负责人:
      Jie Gu
    • 依托单位:
    SHF: Small: A Chip of Happiness: Device-to-System Developments of Affective Computing for Human-in-the-loop Computer System
    • 批准号:
      2208573
    • 项目类别:
      Standard Grant
    • 资助金额:
      $60.0万
    • 财政年份:
      2022
    • 负责人:
      Jie Gu
    • 依托单位:
    SHF: Small: Development of Differentiable Memory Augmented Neural CPU Architecture for Cognitive Computing
    • 批准号:
      2008906
    • 项目类别:
      Standard Grant
    • 资助金额:
      $50.0万
    • 财政年份:
      2020
    • 负责人:
      Jie Gu
    • 依托单位:
    CAREER: Design and Synthesis of Energy-efficient Time-domain Computing for Intelligent Edge Processing
    • 批准号:
      1846424
    • 项目类别:
      Continuing Grant
    • 资助金额:
      $100.0万
    • 财政年份:
      2019
    • 负责人:
      Jie Gu
    • 依托单位:
    国内基金
    海外基金
    昼夜节律性small RNA在血斑形成时间推断中的法医学应用研究
    • 批准号:
    • 项目类别:
      省市级项目
    • 资助金额:
      --
    • 批准年份:
      2024
    • 负责人:
    • 依托单位:
    tRNA-derived small RNA上调YBX1/CCL5通路参与硼替佐米诱导慢性疼痛的机制研究
    • 批准号:
    • 项目类别:
      省市级项目
    • 资助金额:
      10.0万元
    • 批准年份:
      2022
    • 负责人:
      张祥忠
    • 依托单位:
    Small RNA调控I-F型CRISPR-Cas适应性免疫性的应答及分子机制
    Small RNAs调控解淀粉芽胞杆菌FZB42生防功能的机制研究
    • 批准号:
      31972324
    • 项目类别:
      面上项目
    • 资助金额:
      58.0万元
    • 批准年份:
      2019
    • 负责人:
      高学文
    • 依托单位: