SHF: Small: The Compiler-Architecture Solution to the Data Dependent, Circuit-Level Critical-Paths Variations

计算性能转化为创新的机会，对我们的社会产生积极影响。系统在过去经历了稳定的性能改进。不幸的是，最近半导体工业的发展使这一进步难以维持，这减缓了科学和工程的创新。系统性能取决于所使用的编译器和底层计算机体系结构的能力。通常，编译器可以在指令粒度上控制系统活动，而底层体系结构隐藏更细粒度的信息。然而，编译器无法访问细粒度信息，这限制了将来系统中可获得的总体性能。该项目的新颖之处在于新的编译器和计算机体系结构协同设计，后者使前者能够以比以前探索的更精细的粒度控制活动。这允许底层计算机架构自动提高整体系统性能并节省能源。该项目的影响是使程序员能够自动地更好地利用商品处理器。随着处理器性能的提高，社会将从涉及计算的所有领域的生产力和创新中受益。计算机体系结构的最新发展在单芯片核心数量上取得了巨大的进步，同时加速器带来了显著的性能优势。然而，Amdahl定律提醒我们，单线程执行将永远是系统性能的限制因素——考虑到处理器行业已经远远落后于几十年前的顺序代码性能增长趋势，这是一个可怕的警告。研究小组发现，一个重要的性能障碍是在子周期域，其中电路级关键路径延迟取决于计算的数据。本项目设计了一个与底层架构共同设计的新编译器，用于访问和控制依赖于数据的电路级关键路径延迟。这种设计的影响是消除了在整个计算频谱中广泛使用的商用处理器的计算堆栈中的子周期性能低下，从移动到高性能计算。项目产生的代码、数据和结果将在网站上公开保存：http://users.cs.northwestern.edu/~simonec/SCDVCA.htmlThis奖励反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

Computing performance translates to opportunities for innovations, which positively impact our society. Systems have experienced a steady performance improvement in the past. Unfortunately, recent developments in the semiconductor industry have made this progress hard to maintain, which has slowed down innovations in science and engineering. System performance depends on the capabilities of the compiler used and the underlying computer architecture. Usually, a compiler can control system activities at the instruction granularity while the underlying architecture hides finer-grained information. The compiler's inability to access fine-grained information, however, limits the overall performance obtainable in future systems. The project's novelty is a new compiler and computer architecture co-design where the latter enables the former to control activities at a much finer granularity compared to what has been explored before. This allows the underlying computer architecture to automatically boost the overall system performance as well as to save energy. The project's impact is to enable programmers to automatically make better use of the commodity processors. With processor performance increased, society will benefit from increased productivity and innovation in all areas involving computation. Recent developments in computer architecture have generated tremendous advances in single-chip core count as well as remarkable performance benefits brought by accelerators. However, Amdahl's Law reminds us that single-thread execution will always be the limiting factor for system performance -- a dire warning considering that the processor industry has fallen well short of the decades old sequential code performance growth trend. The team of researchers found that an important performance roadblock is in the sub-cycle domain where the circuit-level critical path latency depends on the data computed. This project designs a new compiler co-designed with the underlying architecture to access and control data-dependent, circuit-level critical path latencies. The impact of this design is the elimination of sub-cycle performance inefficiencies across the computation stack for commodity processors widely used in the whole computing spectrum, ranging from mobile to high performance computing. Code, data, and results emanating from the project will be maintained publicly at the website: http://users.cs.northwestern.edu/~simonec/SCDVCA.htmlThis award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.