FoMR: IPC Improvement through Hardware Memorization

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Although chip manufacturers continue to increase the number of transistors that can fit into a single computer chip, making use of these additional transistors to improve performance of new computers is increasingly more challenging. In the past several years, the pace of performance improvements of each generation of computer processors have come down, with the traditional techniques for improving performance reaching diminishing returns. This work develops Speculative Memoization, a new technique with potential to more effectively use additional transistors for improving processor performance. Speculative Memoization can enable significant increases in the performance of future computers, increasing user productivity and providing more immersive user experiences.Traditional ways of improving processor performance targeted increasing the sizes of on-chip buffers, such as caches, re-order buffers, and branch predictors. Increasing the buffer sizes offers some performance improvement, but does not reduce the total work done by the processor. Instead, Speculative Memoization offers a radical alternative, identifying repeating work that the processor has already done and avoiding redundant execution, therefore, improving performance by reducing the total amount of work done by the processors. This work explores the limits of performing memoization in hardware, proposes designs for the hardware memoization mechanisms, and works to mitigate the compiler and system software effects on such memorization.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.