CRII: FET: Ferroelectric FET based flexible circuits and system design

当前的计算系统在处理具有快速增长的数据存储和处理需求的应用方面面临重大挑战。这意味着需要高效和密集的数据存储。多电平单元(MLC)是能够在单个设备中存储多于一位信息的存储单元，因此可用于密集高效存储。然而，在传统的计算系统中，存储在内存中的数据需要传输到计算单元进行处理，导致过高的功耗和延迟。因此，需要一种限制数据移动、进行有效的数据传输并处理与MLC存储器相关的挑战的计算范例。该项目研究如何将新兴技术设计融入到现有的基于互补金属氧化物半导体(CMOS)的计算系统中，以满足上述要求。从这个项目中学到的知识和见解将被纳入计算机工程本科和研究生课程。调查员还将让来自代表性不足群体的学生和本科生参与这个项目。研究人员选择了一种名为铁电场效应晶体管(FeFET)的新兴器件技术，该项目将专注于两项具体的研究任务。第一个任务是开发符合传统单层单元和密集多层单元(MLC)存储体系结构的电路元件。MLC单元通过利用特定的设备属性来存储多个位，并且MLC数据到二进制的转换需要复杂的外围电路。本项目旨在通过利用FeFET的阈值电压可编程性来设计紧凑灵活的外围电路。在第二个任务中，研究人员将利用FeFET的结构特征来设计灵活的多方向数据存取存储器和缓存。表现出行-列方向偏好的应用程序，例如矩阵操作和数据库操作，将特别受益于灵活的定向访问系统，因为它限制了从存储器到处理单元的不必要的数据传输。研究人员还将探索将灵活的外围设备重新用于现场计算，以进一步限制数据传输并提高计算效率。该项目由CESE/CCF部门的新兴技术基础(FET)计划和既定的激励竞争研究计划(EPSCoR)共同资助。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Current computing systems face major challenges in dealing with applications, having rapidly increasing data storage and processing requirements. This implies the need for efficient and dense data storage. A multi-level cell (MLC) is a memory cell capable of storing more than a single bit of information in a single device, and thus can be used for dense efficient storage. However in conventional computing systems, data stored in memory needs to get transferred to computing units for processing, resulting in excessive power dissipation and delay. Therefore, there exists a need for a computing paradigm that limits data movement, does efficient data transfer and handles the challenges associated with MLC memories. This project investigates the incorporation of emerging technology designs into existing Complementary Metal Oxide Semiconductor (CMOS) based computing systems to satisfy the above-mentioned requirements. Learnings and insights developed from this project will be incorporated into computer-engineering undergraduate and graduate courses. Investigator will also involve students from underrepresented groups and undergraduate students in this project. Investigator chooses an emerging device technology called ferroelectric field-effect transistor (FeFET), and the project will focus on two specific research tasks. The first task will develop circuit components amenable to traditional single-level cell and dense multi-level cell (MLC) memory architectures. MLC cells store multiple bits by exploiting a particular device property and MLC data to binary conversion requires complex peripheral circuits. This project aims to design compact flexible peripheral circuits by leveraging the threshold voltage programmability of FeFETs. In the second task, investigator will utilize the structural features of FeFET to design flexible multi-directional data access memories and caches. Applications exhibiting row-column directional preferences such as matrix operations and database operations will especially benefit from a flexible directional access system as it limits the unnecessary data transfer from memory to processing units. Investigator will also explore the reuse of flexible peripherals for in-situ computing to further limit the data transfer and to increase the computing efficiency.This project is jointly funded by the Foundations of Emerging Technology (FET) program of CISE/CCF Division, and the Established Program to Stimulate Competitive Research (EPSCoR).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.