IMPLEMENTATION OF QUATERNARY CMOS INTEGRATED CIRCUIT FOR DOUBLE MATCHING ALGORITHM AND ITS APPLICATION TO MULTIPLE-VALUED DIGITAL PROCESSING SYSTEM

在本项目中，提出了一种互补通门(CP门)作为多值数字处理系统的基本构建块。一个CP门由两个通过晶体管和一个用多能级离子注入实现的下向文字电路组成。通过SPICE2仿真验证了该四值CP门的特性。模拟中使用的参数来自东北大学10微米的工艺实验。作为四值CP门的实际应用，设计并实现了一种基于模式匹配运算的图像处理器。这里采用的图像处理算法是基于元胞逻辑运算的，该运算以数字方式执行，将4值输入数据的数组转换成新的数据数组。对于具有4级或颜色的图像，每个像素可以直接用单个四进制数字来表示。本文提出的四值图像处理器是基于近邻操作的，由采用新的双匹配算法的模式匹配(PM)单元组成。实际上，用于3x3近邻逻辑运算的图像处理器是在东北大学用具有10微米设计规则的四值CMOS集成电路制造的。结果，由于采用四值CP门的四值逻辑系统减少了互连和双重匹配算法，因此可以实现高度紧凑的图像处理器。此外，所获得的图像处理器在功耗和运算速度方面优于传统的二进制处理器。

In this project a complementary pass gate ( CP-gate ) is proposed as a basic building block for a multiple-valued digital processing system. A CP-gate is composed of two pass transistors and a down literal circuit realized with multiple-level ion implants. The characteristic of the quaternary CP-gate is confirmed by simulation with SPICE2. The parameter used in the simulation are obtained from experiments of 10 mum CMOS process at Tohoku University. Consequently it is seen that the quaternary CP-gate has attractive features of high integration density and low power density.As a practical application of the quaternary CP-gate, a image processor based on the pattern matching operation is designed and implemented. The image processing algorithm employed here is based on cellular logic operations which perform digitally to transform an array of 4-valued input data into a new data array. With image having 4-levels or colors, each pixel can be directly expressed by a single quaternary digit. The quaternary image processor presented here is based on the near-neighbor operations, and consists of the pattern matching (PM) cells using new double matching algorithm. Actually, the image processor for 3 x 3 near neighbor logic operation is fabricated in quaternary CMOS integrated circuits with 10 mum design rules at Tohoku University. As a result, a highly compact image processor can be realized because of the reduction of interconnections and double matching algorithm of the quaternary logic system using the quaternary CP-gates. Moreover, the image processor obtained is superior to a conventional binary processor in dissipation power and operation speed.