IMPLEMENTATION OF QUATERNARY CMOS INTEGRATED CIRCUIT FOR DOUBLE MATCHING ALGORITHM AND ITS APPLICATION TO MULTIPLE-VALUED DIGITAL PROCESSING SYSTEM

本课题提出了一种互补通闸（CP-gate）作为多值数字处理系统的基本组成部分。一个cp门由两个通路晶体管和一个用多层离子植入实现的下行电路组成。采用SPICE2进行仿真，验证了四元cp栅极的特性。模拟中所用的参数是由日本东北大学的10 μ m CMOS工艺实验得到的。由此可见，四元cp栅极具有高积分密度和低功率密度的特点。作为四元cp门的实际应用，设计并实现了一种基于模式匹配运算的图像处理器。本文所采用的图像处理算法基于元胞逻辑运算，其以数字方式将4值输入数据数组转换为新的数据数组。图像具有4级或4种颜色，每个像素可以直接用一个四位数字表示。本文提出的四元图像处理器基于近邻运算，并采用新的双匹配算法由模式匹配单元组成。实际上，用于3 × 3近邻逻辑运算的图像处理器是由日本东北大学在四元CMOS集成电路中制造的，具有10个设计规则。因此，由于采用四元cp门的四元逻辑系统减少了互连和双重匹配算法，可以实现高度紧凑的图像处理器。此外，所得到的图像处理器在耗散功率和运算速度上都优于传统的二进制处理器。

In this project a complementary pass gate ( CP-gate ) is proposed as a basic building block for a multiple-valued digital processing system. A CP-gate is composed of two pass transistors and a down literal circuit realized with multiple-level ion implants. The characteristic of the quaternary CP-gate is confirmed by simulation with SPICE2. The parameter used in the simulation are obtained from experiments of 10 mum CMOS process at Tohoku University. Consequently it is seen that the quaternary CP-gate has attractive features of high integration density and low power density.As a practical application of the quaternary CP-gate, a image processor based on the pattern matching operation is designed and implemented. The image processing algorithm employed here is based on cellular logic operations which perform digitally to transform an array of 4-valued input data into a new data array. With image having 4-levels or colors, each pixel can be directly expressed by a single quaternary digit. The quaternary image processor presented here is based on the near-neighbor operations, and consists of the pattern matching (PM) cells using new double matching algorithm. Actually, the image processor for 3 x 3 near neighbor logic operation is fabricated in quaternary CMOS integrated circuits with 10 mum design rules at Tohoku University. As a result, a highly compact image processor can be realized because of the reduction of interconnections and double matching algorithm of the quaternary logic system using the quaternary CP-gates. Moreover, the image processor obtained is superior to a conventional binary processor in dissipation power and operation speed.