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IMPLEMENTATION OF QUATERNARY CMOS INTEGRATED CIRCUIT FOR DOUBLE MATCHING ALGORITHM AND ITS APPLICATION TO MULTIPLE-VALUED DIGITAL PROCESSING SYSTEM

四进制CMOS集成电路双匹配算法的实现及其在多值数字处理系统中的应用

基本信息

批准号：
63850083
负责人：
HIGUCHI Tatsuo
金额：
$ 2.05万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research
财政年份：
1988
资助国家：
日本
起止时间：
1988 至 1989
项目状态：
已结题

项目摘要

In this project a complementary pass gate ( CP-gate ) is proposed as a basic building block for a multiple-valued digital processing system. A CP-gate is composed of two pass transistors and a down literal circuit realized with multiple-level ion implants. The characteristic of the quaternary CP-gate is confirmed by simulation with SPICE2. The parameter used in the simulation are obtained from experiments of 10 mum CMOS process at Tohoku University. Consequently it is seen that the quaternary CP-gate has attractive features of high integration density and low power density.As a practical application of the quaternary CP-gate, a image processor based on the pattern matching operation is designed and implemented. The image processing algorithm employed here is based on cellular logic operations which perform digitally to transform an array of 4-valued input data into a new data array. With image having 4-levels or colors, each pixel can be directly expressed by a single quaternary digit. The quaternary image processor presented here is based on the near-neighbor operations, and consists of the pattern matching (PM) cells using new double matching algorithm. Actually, the image processor for 3 x 3 near neighbor logic operation is fabricated in quaternary CMOS integrated circuits with 10 mum design rules at Tohoku University. As a result, a highly compact image processor can be realized because of the reduction of interconnections and double matching algorithm of the quaternary logic system using the quaternary CP-gates. Moreover, the image processor obtained is superior to a conventional binary processor in dissipation power and operation speed.

在这个项目中，互补通过门（CP门）提出了作为一个基本的多值数字处理系统的构建块。CP门由两个传输晶体管和一个用多级离子注入实现的下向电路组成。四元CP门的特性通过SPICE 2仿真得到了证实。模拟中使用的参数是从东北大学的10妈妈CMOS工艺的实验中获得的。作为四元CP门的一个实际应用，设计并实现了一个基于模式匹配运算的图像处理器。这里采用的图像处理算法是基于细胞逻辑运算，其数字地执行以将4值输入数据的阵列变换成新的数据阵列。对于具有4级或4种颜色的图像，每个像素可以直接由单个四进制数字表示。本文提出的四元图像处理器基于近邻操作，由采用新的双匹配算法的模式匹配（PM）单元组成。实际上，用于3 × 3近邻逻辑操作的图像处理器是在东北大学采用10 μ m设计规则的四元CMOS集成电路中制造的。结果，由于使用四元CP门的四元逻辑系统的互连和双匹配算法的减少，可以实现高度紧凑的图像处理器。此外，所获得的图像处理器在功耗和运算速度方面上级传统的二进制处理器。