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Development of Configurable Signal Processors Using Redundant Arithmetic Algorithms

使用冗余算术算法开发可配置信号处理器

基本信息

批准号：
11558028
负责人：
HIGUCHI Tatsuo
金额：
$ 7.55万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1999
资助国家：
日本
起止时间：
1999 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-11558028/
关键词：
Hardware Algorithms Integrated Circuits VLSI Datapaths Arithmetic Algorithms Redundant Number System FPGA Digital Signal Processing デイジタル信号処理

项目摘要

Application specific ICs (ASICs) play an important role in present-day DSP technology. However, the ASIC technology requires significant time and cost for development, and is lacking the flexibility in design modification. The FPGA (Field-Programmable Gate Array) technology, on the other hand, attracts much attention recently due to its rapid prototyping capability, but it is difficult to apply FPGAs to high-performance systems. This research project is to develop configurable signal processors --- DSP-oriented FPGA architectures employing redundant arithmetic alogorithms for achieving both high-performance and programmabiligy. Listed below are major results of this project:1. A configurable signal processor IC, that can implement high-frequency FIR filters with 10--100 MHz sampling rate, was developed. The test chip integrates redundant SW adders and can implement FIR filters of order up to 11. Assuming the use of state-of-the-art CMOS technology, the proposed architecture could be applied to QAM modulators/demodulators and format converters for digital TV applications, for example.2. A configurable signal processor IC (for FIR filtering) using current-mode multiple-valued logic technology was developed, where 5-level bi-directional current signals are used for intra-chip communication. The use of multiple-valued logic makes possible to reduce the chip area by 50% and power consumption by 4-40%.3. Various redundant arithmetic algorithms for DSP applications are systematically investigated. Also, new CAD techniques were developed for designing/verifying/synthesizing signal processors using redundant arithmetic algorithms.4. A new fault-tolerant FPGA architecture that can detect hardware faults and reconfigure its architecture to recover the correct function was proposed for use in mission-critical applications.

专用 IC (ASIC) 在当今 DSP 技术中发挥着重要作用。然而，ASIC技术需要大量的开发时间和成本，并且缺乏设计修改的灵活性。另一方面，FPGA（现场可编程门阵列）技术近年来因其快速原型设计能力而备受关注，但将FPGA应用到高性能系统中却存在困难。该研究项目旨在开发可配置信号处理器——面向DSP的FPGA架构，采用冗余算术算法来实现高性能和可编程性。本项目的主要成果如下： 1．开发了一种可配置的信号处理器 IC，可以实现采样率为 10--100 MHz 的高频 FIR 滤波器。该测试芯片集成了冗余SW加法器，可以实现高达11阶的FIR滤波器。假设使用最先进的CMOS技术，所提出的架构可以应用于数字电视应用的QAM调制器/解调器和格式转换器。2．开发了一种采用电流模式多值逻辑技术的可配置信号处理器IC（用于FIR滤波），其中5电平双向电流信号用于片内通信。采用多值逻辑可以使芯片面积减少50%，功耗减少4-40%。3．系统地研究了DSP 应用的各种冗余算法。此外，还开发了新的CAD技术，用于使用冗余算术算法设计/验证/合成信号处理器。4．提出了一种新的容错 FPGA 架构，可以检测硬件故障并重新配置其架构以恢复正确的功能，用于关键任务应用。