Development of Configurable Signal Processors Using Redundant Arithmetic Algorithms

专用集成电路(ASIC)在当今的数字信号处理技术中扮演着重要的角色。然而，ASIC技术的开发需要大量的时间和成本，并且在设计修改方面缺乏灵活性。另一方面，现场可编程门阵列(现场可编程门阵列)技术由于其快速成型能力而备受关注，但其在高性能系统中的应用一直是个难题。本研究项目旨在开发可配置的信号处理器-采用冗余算术算法实现高性能和可编程性的面向DSP的FPGA体系结构。本课题的主要成果如下：1.研制了一款可配置的信号处理芯片，可以实现10-100 MHz采样率的高频FIR滤波器。该测试芯片集成了冗余的软件加法器，可以实现高达11阶的FIR滤波器。假设使用最先进的CMOS工艺，所提出的结构可以应用于数字电视应用中的QAM调制解调器和格式转换器。采用电流型多值逻辑技术设计了一种可配置的信号处理器芯片(用于FIR滤波)，其中5电平双向电流信号用于片内通信。使用多值逻辑可以使芯片面积减少50%，功耗减少4%-40%。系统地研究了适用于数字信号处理器的各种冗余算法。此外，还开发了新的CAD技术，用于使用冗余算术算法设计/验证/综合信号处理器。提出了一种新的容错结构，该结构可以检测硬件故障并重新配置其结构以恢复正确的功能，用于任务关键型应用。

Application specific ICs (ASICs) play an important role in present-day DSP technology. However, the ASIC technology requires significant time and cost for development, and is lacking the flexibility in design modification. The FPGA (Field-Programmable Gate Array) technology, on the other hand, attracts much attention recently due to its rapid prototyping capability, but it is difficult to apply FPGAs to high-performance systems. This research project is to develop configurable signal processors --- DSP-oriented FPGA architectures employing redundant arithmetic alogorithms for achieving both high-performance and programmabiligy. Listed below are major results of this project:1. A configurable signal processor IC, that can implement high-frequency FIR filters with 10--100 MHz sampling rate, was developed. The test chip integrates redundant SW adders and can implement FIR filters of order up to 11. Assuming the use of state-of-the-art CMOS technology, the proposed architecture could be applied to QAM modulators/demodulators and format converters for digital TV applications, for example.2. A configurable signal processor IC (for FIR filtering) using current-mode multiple-valued logic technology was developed, where 5-level bi-directional current signals are used for intra-chip communication. The use of multiple-valued logic makes possible to reduce the chip area by 50% and power consumption by 4-40%.3. Various redundant arithmetic algorithms for DSP applications are systematically investigated. Also, new CAD techniques were developed for designing/verifying/synthesizing signal processors using redundant arithmetic algorithms.4. A new fault-tolerant FPGA architecture that can detect hardware faults and reconfigure its architecture to recover the correct function was proposed for use in mission-critical applications.