Development of Configurable Signal Processors Using Redundant Arithmetic Algorithms

专用集成电路（ASIC）在当今的DSP技术中扮演着重要的角色。然而，ASIC技术需要大量的时间和成本用于开发，并且缺乏设计修改的灵活性。另一方面，FPGA（现场可编程门阵列）技术由于其快速原型化能力而最近引起了很多关注，但是很难将FPGA应用于高性能系统。本研究计画旨在发展可组态式信号处理器-以DSP为核心之FPGA架构，并采用冗余演算法，以达到高效能与可程式化之目的。以下是本项目的主要成果：1.研制了一种可配置的信号处理器集成电路，可实现10--100MHz采样率的高频FIR滤波器。测试芯片集成了冗余SW加法器，可以实现阶数高达11的FIR滤波器。假设使用最先进的CMOS技术，所提出的架构可以应用于QAM调制器/解调器和数字电视应用的格式转换器，例如。设计了一种基于电流模式多值逻辑技术的可配置信号处理器（FIR滤波）芯片，芯片内部通信采用5电平双向电流信号。多值逻辑的使用使芯片面积减少50%，功耗降低4- 40%。系统地研究了DSP应用中的各种冗余算法。此外，还开发了新的CAD技术，用于设计/验证/综合使用冗余算术算法的信号处理器.提出了一种新的容错FPGA结构，它可以检测硬件故障并重新配置其结构以恢复正确的功能，用于关键任务应用。

Application specific ICs (ASICs) play an important role in present-day DSP technology. However, the ASIC technology requires significant time and cost for development, and is lacking the flexibility in design modification. The FPGA (Field-Programmable Gate Array) technology, on the other hand, attracts much attention recently due to its rapid prototyping capability, but it is difficult to apply FPGAs to high-performance systems. This research project is to develop configurable signal processors --- DSP-oriented FPGA architectures employing redundant arithmetic alogorithms for achieving both high-performance and programmabiligy. Listed below are major results of this project:1. A configurable signal processor IC, that can implement high-frequency FIR filters with 10--100 MHz sampling rate, was developed. The test chip integrates redundant SW adders and can implement FIR filters of order up to 11. Assuming the use of state-of-the-art CMOS technology, the proposed architecture could be applied to QAM modulators/demodulators and format converters for digital TV applications, for example.2. A configurable signal processor IC (for FIR filtering) using current-mode multiple-valued logic technology was developed, where 5-level bi-directional current signals are used for intra-chip communication. The use of multiple-valued logic makes possible to reduce the chip area by 50% and power consumption by 4-40%.3. Various redundant arithmetic algorithms for DSP applications are systematically investigated. Also, new CAD techniques were developed for designing/verifying/synthesizing signal processors using redundant arithmetic algorithms.4. A new fault-tolerant FPGA architecture that can detect hardware faults and reconfigure its architecture to recover the correct function was proposed for use in mission-critical applications.