Development of Configurable Signal Processors Using Redundant Arithmetic Algorithms

专用集成电路（asic）在当今的DSP技术中起着重要的作用。然而，ASIC技术的开发需要大量的时间和成本，并且缺乏设计修改的灵活性。另一方面，FPGA （Field-Programmable Gate Array，现场可编程门阵列）技术由于其快速成型的能力近年来备受关注，但它很难应用于高性能系统。这个研究项目是开发可配置的信号处理器——面向dsp的FPGA架构，采用冗余算法来实现高性能和可编程性。以下是本项目的主要成果：开发了一种可配置的信号处理器IC，可实现采样率为10—100 MHz的高频FIR滤波器。测试芯片集成了冗余的SW加法器，可以实现多达11阶的FIR滤波器。假设使用最先进的CMOS技术，所提出的架构可以应用于数字电视应用的QAM调制器/解调器和格式转换器，例如2。采用电流模式多值逻辑技术开发了一种可配置的信号处理器IC（用于FIR滤波），其中5级双向电流信号用于片内通信。使用多值逻辑可以将芯片面积减少50%，功耗减少4-40%。系统地研究了DSP应用中的各种冗余算法。此外，利用冗余算法设计/验证/合成信号处理器的新的CAD技术也得到了发展。提出了一种新的容错FPGA架构，该架构可以检测硬件故障并重新配置其架构以恢复正确的功能，用于关键任务应用。

Application specific ICs (ASICs) play an important role in present-day DSP technology. However, the ASIC technology requires significant time and cost for development, and is lacking the flexibility in design modification. The FPGA (Field-Programmable Gate Array) technology, on the other hand, attracts much attention recently due to its rapid prototyping capability, but it is difficult to apply FPGAs to high-performance systems. This research project is to develop configurable signal processors --- DSP-oriented FPGA architectures employing redundant arithmetic alogorithms for achieving both high-performance and programmabiligy. Listed below are major results of this project:1. A configurable signal processor IC, that can implement high-frequency FIR filters with 10--100 MHz sampling rate, was developed. The test chip integrates redundant SW adders and can implement FIR filters of order up to 11. Assuming the use of state-of-the-art CMOS technology, the proposed architecture could be applied to QAM modulators/demodulators and format converters for digital TV applications, for example.2. A configurable signal processor IC (for FIR filtering) using current-mode multiple-valued logic technology was developed, where 5-level bi-directional current signals are used for intra-chip communication. The use of multiple-valued logic makes possible to reduce the chip area by 50% and power consumption by 4-40%.3. Various redundant arithmetic algorithms for DSP applications are systematically investigated. Also, new CAD techniques were developed for designing/verifying/synthesizing signal processors using redundant arithmetic algorithms.4. A new fault-tolerant FPGA architecture that can detect hardware faults and reconfigure its architecture to recover the correct function was proposed for use in mission-critical applications.